Abstract: A method for determining an integrity of an execution of a code fragment is provided. The method includes identifying a reference signature for the code fragment within an abstracted representation of a program code comprising the code fragment. Further, the method includes executing the code fragment and determining a signature of the executed code fragment. The method includes comparing the signature with the reference signature.

Abstract: A method for determining an integrity of an execution of a code fragment is provided. The method includes identifying a reference signature for the code fragment within an abstracted representation of a program code comprising the code fragment. Further, the method includes executing the code fragment and determining a signature of the executed code fragment. The method includes comparing the signature with the reference signature.

Abstract: A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a succession of instruction words having address information, the succession of instruction words prescribing a sequence of machine words which are intended to be processed by an arithmetic and logic unit which is coupled to a buffer store, altering the association between at least a portion of the set of machine words and at least a portion of the set of addresses, changing the address information in the succession of instruction words based on the alteration of the association, storing the changed succession of instruction words in a memory, and storing the set of machine words in the memory, so that it is possible to access the machine words using the associated addresses.

Abstract: A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump command. The processor has a command processor, which is adapted in the mother program upon occurrence of the sub-program jump command, to extract back-up information about data required in the mother program after processing the sub-program from the sub-program jump command, to back-up data required in the mother program after execution of the sub-program based on the back-up information, to extract a destination address from the sub-program jump command, which refers to the sub-program, and to effect the continuation of the processing of the program with the sub-program based on the destination address.

Abstract: A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a succession of instruction words having address information, the succession of instruction words prescribing a sequence of machine words which are intended to be processed by an arithmetic and logic unit which is coupled to a buffer store, altering the association between at least a portion of the set of machine words and at least a portion of the set of addresses, changing the address information in the succession of instruction words based on the alteration of the association, storing the changed succession of instruction words in a memory, and storing the set of machine words in the memory, so that it is possible to access the machine words using the associated addresses.

Abstract: A data processing method and system including a processor, a user data storage medium, and a management data storage medium, wherein the management data are used to manage the user data.

Abstract: A parallel data bus having a plurality of bus lines, and a bus mode switching device for switching between data transmission at a high data transmission rate and data transmission at high data integrity.

Abstract: Method and system for operating a cache memory. The method includes the steps of splitting the cache memory into sets, addressing the cache memory using a processor address which is split into at least two fields, and forming one of the fields of the processor address for addressing the cache memory from a combinational logic function on a basis of a modulo N operation, where N corresponds to the number of sets in the cache memory.

Abstract: A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump command. The processor has a command processor, which is adapted in the mother program upon occurrence of the sub-program jump command, to extract back-up information about data required in the mother program after processing the sub-program from the sub-program jump command, to back-up data required in the mother program after execution of the sub-program based on the back-up information, to extract a destination address from the sub-program jump command, which refers to the sub-program, and to effect the continuation of the processing of the program with the sub-program based on the destination address.

Abstract: A method for securing a multi-dimensionally constructed chip stack, which has a plurality of part chips which are interconnected at respective contact areas and of which at least one contains functional components, includes the steps of providing respective conductor tracks in the part chips and providing feed-through contacts at the respective contact areas, which in each case interconnect conductor tracks of various part chips so that a continuous electrical signal path running through the part chips is formed. An electrical signal is transmitted from a transmitting device provided at a first end of the electrical signal path to a receiving device provided at a second end of the electrical signal path. When the electrical signal cannot be received, it is determined that the chip stack has been damaged. A device for securing a chip stack and a chip configuration are also provided.

Abstract: A cache memory serves for accelerating accesses to an external memory of a microprocessor. Instead of an actually occurring hit event, a cache miss is signaled to the microprocessor. The reversal is randomly controlled. This disguises the current profile of cache hit and miss events, which enhances the security against statistical attack techniques based on the evaluation of the current profile.

Abstract: An integrated circuit with at least one antenna for the contactless transmission of data or energy. The antenna is configured above and/or below circuit sections to be protected and, as part of a protective circuit, enables the integrated circuit to be monitored with regard to an undesirable external attack. Such an attack can be identified by the attempt to effect observation or manipulation from the outside, which are typically associated with an alteration of the physical properties of the antenna. These physical alterations lead to significant changes in the protective circuit signals that are transmitted via the antenna. These changes are identified by signal detectors and initiate a transfer of the integrated circuit into a security mode. In this case, in addition to the function as means for transmitting data and/or energy, the antenna also serves the function of being a protective shield of a protective circuit for the integrated circuit.

Abstract: A circuit configuration with a deactivatable scan path, includes a number of function blocks each connected to at least one other of the function blocks. At least one sub-set of the connections is in the form of a respective interlocking element which can be switched through an activation line (Scan Enable) from a normal mode to a test mode and which has a further data input and data output. The further data inputs and outputs are connected to one another by data line sections in such a manner that the interlocking elements form a shift register which provides a scan path. At least one electrically programmable protection element, which either interrupts a given line or connects it to a defined potential, is disposed along the activation line (Scan Enable) and/or the data line sections.

Abstract: A data processing method where data to be processed is feed to a processing unit. Supplying a current to the processing unit for operating the processing unit and supplying in a randomly controlled manner a part of the current fed to the processing unit, to an auxiliary circuit.

Abstract: A method for securing a multi-dimensionally constructed chip stack, which has a plurality of part chips which are interconnected at respective contact areas and of which at least one contains functional components, includes the steps of providing respective conductor tracks in the part chips and providing feed-through contacts at the respective contact areas, which in each case interconnect conductor tracks of various part chips so that a continuous electrical signal path running through the part chips is formed. An electrical signal is transmitted from a transmitting device provided at a first end of the electrical signal path to a receiving device provided at a second end of the electrical signal path. When the electrical signal cannot be received, it is determined that the chip stack has been damaged. A device for securing a chip stack and a chip configuration are also provided.

Abstract: A cache memory serves for accelerating accesses to an external memory of a microprocessor. Instead of an actually occurring hit event, a cache miss is signaled to the microprocessor. The reversal is randomly controlled. This disguises the current profile of cache hit and miss events, which enhances the security against statistical attack techniques based on the evaluation of the current profile.

Abstract: The invention is directed to a protective circuit for an integrated circuit 1. This protective circuit is preferably arranged in a plurality of circuit levels 2, 3 under and/or above the intergrated circuit 1. It exhibits a plurality of interconnects 10, 11 that are charged with different signals of one or more signal generators. The different signals, after traversing the interconnects 10, 11, are analyzed with one or more detectors in that the signals received by detectors are respectively compared to rated reference signals, and an alarm signal is forwarded to the integrated circuit given the presence of a significant difference. On the basis of this alarm signal, the integrated circuit is switched into a security mode that makes an analysis or a manipulation of the integrated circuit practically impossible.

Abstract: A semiconductor chip having circuits which are produced in at least one layer of a semiconductor substrate and are arranged in at least one group. The semiconductor chip has at least one conductive protective layer which is arranged above at least one such circuit group and is electrically connected to at least one of the circuits. The substrate has at least one protective sensor, and the detection connection(s) of the protective sensor/protective sensors is/are connected to the conductive protective layer or to at least one of the conductive protective layers. Output connections of the protective sensor/protective sensors are connected to at least one of the circuits such that the circuit(s) cannot operate properly if there is a defined, nonvolatile level at the output of the protective sensor(s).

Abstract: The copy protection system and method combines the features of a conventional electronic data carrier with a dongle to form a secure storage medium. The storage medium has a unique identification, such as a device serial number. The host transmits a challenge signal to the storage medium and then checks the response received from the storage medium for a proper correlation between the useful data and the storage medium. A mismatch indicates that the data is present on a bootleg carrier instead of on its authorized carrier. Therefore, if the response signal in the challenge-response process does not correspond to the expected setpoint response, then the data are not authorized for processing.

Abstract: The power supply device has a temporary energy store, a main energy store, and a switching device. The switching device has three switching states. The temporary energy store is connected in the first switching state to a power supply input and is connected in the second switching state to the main energy store, which is connected to a power supply output. An energy discharge device is connected to the temporary energy store in the third switching state of the switching device which follows directly the second switching state.