Abstract: The invention relates to a method for producing a methane-rich product gas, in which a starting gas containing hydrogen and carbon dioxide is catalytically methanated under the influence of at least one adjustatable parameter in at least two stages and at least one criterion relating to the composition of the product gas is monitored. The criterion is fulfilled under a condition influencing the method and when the condition changes, a change in the parameter setting that preserves fulfilment of the criterion is affected.

Abstract: A technique migrates data from source arrays to target arrays. The array devices operate in either active mode, passive mode, or stalled-active mode. The technique involves providing active-to-passive instructions to transition the source devices from active to passive while a host initially accesses host data from the source arrays using MPIO software (the target devices being in stalled-active mode), and monitoring whether the source devices successfully transition to passive during a predefined time period. If so, the technique involves operating the target devices in active mode and transferring data from the source devices to the target devices to enable the host to access the host data from the target arrays using the MPIO software. However, if a source device remains passive, the technique involves providing passive-to-active instructions to transition the source devices back to active to enable the host to access the host data from the source arrays.

Abstract: An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.

Abstract: Described are techniques for processing recovery points. One or more storage objects for which data protection processing is performed are determined. The data protection processing includes copying data for each of said one or more storage objects to one or more data protection storage devices. One or more recovery points corresponding to each of said one or more storage objects are determined. For each of the one or more recovery points corresponding to each of the one or more storage objects, performing processing including determining whether said each recovery point is at least one of recoverable in accordance with recoverable criteria and restartable in accordance with restartable criteria.

Abstract: Described are techniques for processing recovery points. One or more storage objects for which data protection processing is performed are determined. The data protection processing includes copying data for each of said one or more storage objects to one or more data protection storage devices. One or more recovery points corresponding to each of said one or more storage objects are determined. For each of the one or more recovery points corresponding to each of the one or more storage objects, performing processing including determining whether said each recovery point is at least one of recoverable in accordance with recoverable criteria and restartable in accordance with restartable criteria.

Abstract: An energy supply system is provided with an electricity generating device for regeneratively generating electrical energy that can be fed into an electricity supply grid. The energy supply system includes an electricity generating device for regeneratively generating electrical energy which can be fed into an electricity supply grid, a hydrogen generating device for generating hydrogen using electrical energy from the regenerative electricity generating device, a methanation device for converting hydrogen generated by the hydrogen generating device and a supplied carbon oxide gas into a gas containing methane, and a gas providing device for providing a supplementary gas or a replacement gas in a variably specifiable supplementary/replacement gas quality suitable for feeding into a gas supply grid with the use of the gas containing methane from the methanation device and/or the hydrogen from the hydrogen generating device. A method of operating the system is also provided.

Abstract: A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Abstract: An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

Abstract: An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.

Abstract: A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

Abstract: A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.

Abstract: Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

Abstract: The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

Abstract: Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure.

Abstract: The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (106, 108); forming an active region (1) on the substrate a fin-like channel region (113b?; 113b?). Formation of the fin-like channel region (113b?; 113b?) has the following steps: forming a hard mask (S1-S4) on the active region (1); anisotropic etching of the active region (1) using the hard mask (S1-S4) forming STI trenches (G1-G5) having an STI oxide filling (9); polishing-back of the STI oxide filling (9); etching-back of the polished-back STI oxide filling (9); selective removal of components of the hard mask forming a modified hard mask (S1?-S4?); anisotropic etching of the active region (1) using the modified hard mask (S1?-S4?) forming widened STI trenches (G1?-G5?), the fin-like channel regions (113b?; 113b?) of the active region (1) remaining for each individual FinFET transistor.

Abstract: An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.

Abstract: Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.