Abstract: A voltage regulator control circuit includes a transistor input controller. The transistor input controller forces a slew control signal on its slew control output to a state responsive to a change in a load condition and forces an ON signal to a state on its first transistor control output. A first transistor has a first control input and first and second current terminals. A second transistor couples to the first transistor. A driver has a slew control input, a driver input, and a driver output. The driver input couples to the first transistor control output. The driver output couples to the first control input. Responsive to a first logic state of the slew control signal and a first state of the ON signal, the driver provides a higher current to the first control input, and responsive to a second state of the slew control signal and a first state of the ON signal, the driver provides a lower current to the first control input.

Abstract: Control logic for producing a digital input to a digital-to-analog converter (DAC) in a power converter system. The control logic selects from among a plurality of slew rates during a transition of an output voltage in response to a change in the desired setpoint, so that the output voltage transition follows a desired nominal slew rate. In an initial interval of the transition, a steeper slew rate than the nominal slew rate is selected by the control logic for the digital input to the DAC, until the digital input to the DAC exceeds the nominal slew rate by a first parameter value. At that point, a slew clamp is applied to advance the digital input at the nominal slew rate. Upon the digital input approaching the setpoint value to within a second parameter value, a flatter slew rate than nominal is applied.

Abstract: An electronic circuit (300) includes a signal processing circuit (310) including first and second signal processing blocks (310.1, 310.3) coupled in cascade, a memory circuit (320) coupled to and adjustable between the first and second signal processing blocks (310.1, 310.3), the memory circuit (320) having memory spaces, the memory circuit (320) configurable to establish a trade-off of the memory spaces between the first and second signal processing blocks (310.1, 310.3), and a configuring circuit (330) operable to configure the trade-off of the memory spaces of the memory circuit (320).

Abstract: The present invention provides a packet detector for use with a packet-based wireless receiver employing a receive antenna for P concurrently transmitted streams, where P is at least two. In one embodiment, the packet detector includes a correlation unit coupled to the single receive antenna and configured to provide a correlation function based on P acquisition fields corresponding to the P concurrently transmitted streams. Additionally, the packet detector also includes a pseudo-magnitude calculator coupled to the correlation unit and configured to calculate a packet detection metric based on the correlation function.

Abstract: A system for synchronizing a wireless receiver is provided. The system includes a first antenna and a second antenna to receive independent wireless signals containing different combination of data packets. The system includes one or more analyzer components operable to determine correlation metrics based on at least a portion of the first received signal and a portion of the second received signal. The system further includes a synchronization component operable to use the correlation metrics to determine a preferred correlation metric for synchronization by the wireless receiver of the first and second received signals to decode the data packet. A method for synchronizing a receiver of two wireless signals is also provided.

Abstract: A system for synchronizing a wireless receiver is provided. The system includes a first antenna (101a) and a second antenna (101b) to receive wireless signals containing data packets. The system includes one or more analyzer components (156) operable to determine correlation metrics based on at least a portion of the first received signal and a portion of the second received signal. The system further includes a synchronization component (158) operable to use the correlation metrics to determine a preferred correlation metric for synchronization by the wireless receiver of the first and second received signals to decode the data packet. A method for synchronizing a receiver of two wireless signals is also provided.

Abstract: The present invention provides a gain training generator for use with a multiple-input, multiple-output (MIMO) transmitter employing N transmit antennas where N is at least two. In one embodiment, the gain training generator includes a fundamental training encoder configured to provide a basic gain training sequence to one of the N transmit antennas during a time interval to produce a basic gain training waveform having a basic peak-to-average ratio (PAR). Additionally, the gain training generator also includes a supplemental training encoder coupled to the fundamental training encoder and configured to further provide (N?1) supplemental gain training sequences to (N?1) remaining transmit antennas, respectively, during the time interval to produce supplemental gain training waveforms wherein each has a supplemental PAR substantially equal to the basic PAR.

Abstract: A preamble frequency switching design technique for frequency switching the training symbols within the preamble associated with a MIMO communication system ensures that data throughput is optimized.

Abstract: The present invention provides a concurrent gain generator for use with a MIMO transmitter havi'ng an N of two or more transmit antennas. In one embodiment, the concurrent gain generator includes a first sequence formatter that provides one of the N transmit antennas with a gain training sequence during an initial time interval, and a second sequence formatter that further provides (N?1) remaining transmit antennas with (N?1) additional gain training sequences during the initial time interval to train receive gains. The present invention also provides a non-concurrent gain adjuster for use with a MIMO receiver employing an M of two or more receive antennas. In one embodiment, the non-concurrent gain adjuster includes a gain combiner that computes a common receive gain as a function of M independent receive gains, and a gain applier that applies the common receive gain to receivers associated with the M receive antennas.

Abstract: This invention comprises an architecture for voltage mode control of a voice coil motor in a hard disk drive. In contrast to conventional current mode control, coil current is not sensed or measured, which simplifies the feedback design with less hardware required in the implementation. Common design methodologies for the square root velocity profile, linear velocity profile and regulator/estimator control system designs can be migrated from the current mode architecture to the voltage mode architecture.

Abstract: A position sensor includes a stationary platform and a moveable platform. The position sensor further includes at least one beam coupling the moveable platform to the stationary platform. The at least one beam includes piezoresistive material that is positioned tolprovide an indication of a movement of the moveable platform relative to the stationary platform.

Abstract: A position sensor includes a stationary platform and a moveable platform. The position sensor further includes at least one beam coupling the moveable platform to the stationary platform. The at least one beam includes piezoresistive material that is positioned to provide an indication of a movement of the moveable platform relative to the stationary platform.

Abstract: This invention comprises an architecture for voltage mode control of a voice coil motor in a hard disk drive. In contrast to conventional current mode control, coil current is not sensed or measured, which simplifies the feedback design with less hardware required in the implementation. Common design methodologies for the square root velocity profile, linear velocity profile and regulator/estimator control system designs can be migrated from the current mode architecture to the voltage mode architecture.

Abstract: A method for commutation of a switched reluctance motor (SRM) is disclosed that requires no rotor position sensor or detailed prior knowledge of the motor's magnetic characteristics. The apparatus and method employs a calibration routine to learn the flux-current characteristics of each SRM phase in its aligned position. From these characteristics, the flux-current characteristics at other appropriate switching angles are approximated. Commutation is accomplished by estimating the flux in an active phase and comparing the estimate to the flux approximated for the switching angle. The apparatus and method is particularly well suited for relatively heavy duty loading applications, such as a fan.

Abstract: A hard disk drive system (10) includes a rotating magnetic disk (13), an arm (16) moved by a voice coil motor (18), and a read/write head (21) movably supported on the arm by a microactuator (22). The read/write head is moved approximately radially of the disk in response to operation of the microactuator or movement of the arm. The microactuator has a nonlinear transfer function. A control system (62) for controlling the microactuator and the voice coil motor includes a control technique (126) having a nonlinear transfer function which is substantially an inverse of the nonlinear transfer function of the microactuator. Control of the microactuator is effected through the control technique, the control technique linearizing the control of the microactuator.

Abstract: A system for normalizing an infrared detector has two control loops, each of which includes a thermal source and a command system. Each command system controls the temperature of the associated thermal source. Each command system includes an error signal source for providing an error signal indicative of the difference between a commanded temperature for the thermal source and an actual temperature at the thermal source, and includes a compensator coupled between the error signal source and the thermal source. Each compensator includes a first inverse compensation circuit responsive to the error signal for providing an output, a bandwidth maximizing compensation circuit responsive to the output of the first inverse compensation circuit, and a second inverse compensation circuit responsive to an output of the bandwidth maximizing compensation circuit. The thermal source is responsive to the output of the second inverse compensation circuit.