Abstract: For use in data processing systems, an improved controller to control a plurality of peripheral data storage means having different characteristic data transfer rates. The controller has a similar plurality of instruction storage units, a single instruction register, and common operating circuitry for the data storage means. The controller responds to data transfer commands from the system central processor to select an instruction storage unit, and to the characteristic data transfer rate of a selected data storage means sequentially to address instructions within it, at a rate corresponding with the characteristic data transfer rate. The addressed instructions are sequentially output to the instruction register; the common operating circuitry is responsive to the outputs of the instruction register to transfer data as commanded by the central processor.