Patents by Inventor Michel Haond

Michel Haond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10903423
    Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 26, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
    Inventors: Pierre Morin, Michel Haond, Paola Zuliani
  • Publication number: 20200119269
    Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
    Inventors: Pierre MORIN, Michel HAOND, Paola ZULIANI
  • Patent number: 10510955
    Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: December 17, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
    Inventors: Pierre Morin, Michel Haond, Paola Zuliani
  • Publication number: 20180301625
    Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.
    Type: Application
    Filed: April 16, 2018
    Publication date: October 18, 2018
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
    Inventors: Pierre MORIN, Michel HAOND, Paola ZULIANI
  • Patent number: 6812113
    Abstract: The device and process include the deposition of polycrystalline germanium in the interconnect spaces between conductive metal elements. The device and process further include the removal of the germanium in order to form air-filled interconnect spaces.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: November 2, 2004
    Assignee: STMicroelectronics SA
    Inventors: Jerome Alieu, Christophe Lair, Michel Haond
  • Patent number: 6724660
    Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: April 20, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Stephane Monfray, Michel Haond
  • Patent number: 6555482
    Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: April 29, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Malgorzata Jurczak, Michel Haond
  • Patent number: 6537894
    Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: March 25, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Michel Haond, Didier Dutartre
  • Patent number: 6528399
    Abstract: A MOSFET transistor comprising a gate made of silicon-germanium alloy, formed on a single crystal silicon substrate by means of a thin insulating layer, and drain and source regions implanted in the substrate on each side of the gate, characterized in that the gate comprises side regions presenting an increasing germanium percentage towards the sides of the gate facing the drain and source regions. Advantage: compensation of the short channel effect by locally decreasing the work function of the gate material near the drain and source regions.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: March 4, 2003
    Assignee: STMicroelectronics, S.A.
    Inventors: Jérôme Alieu, Caroline Hernandez, Michel Haond
  • Patent number: 6451669
    Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: September 17, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Joaquim Torres, Philippe Gayet, Michel Haond
  • Publication number: 20020097608
    Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.
    Type: Application
    Filed: December 12, 2001
    Publication date: July 25, 2002
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Thomas Skotnicki, Stephane Monfray, Michel Haond
  • Publication number: 20020076899
    Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.
    Type: Application
    Filed: August 1, 2001
    Publication date: June 20, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Michel Haond, Didier Dutartre
  • Publication number: 20010053569
    Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.
    Type: Application
    Filed: March 20, 2001
    Publication date: December 20, 2001
    Applicant: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Malgorzata Jurczak, Michel Haond
  • Publication number: 20010036723
    Abstract: A method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.
    Type: Application
    Filed: December 20, 2000
    Publication date: November 1, 2001
    Inventors: Joaquim Torres, Philippe Gayet, Michel Haond
  • Patent number: 5641704
    Abstract: The semiconductor device includes in a semiconductor substrate (1) at least one predetermined region (6) of the substrate intended subsequently to form an active area, uncovered on its upper surface and situated between lateral trenches (7) containing an insulative material including a layer (9) of a planarising first oxide and at least one underlying layer (8) of a conformal second oxide. The insulative material can form on either side of said uncovered predetermined region (6) of the substrate a boss (16) on the plane upper surface of the device (D) less than 1000 .ANG. high.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: June 24, 1997
    Assignee: France Telecom
    Inventors: Maryse Paoli, Pierre Brouquet, Michel Haond
  • Patent number: 5604149
    Abstract: The semiconductor device comprises in a semiconductor substrate (1) at least one predetermined region (6) of the substrate intended subsequently to form an active area, uncovered on its upper surface and situated between the lateral trenches (7) containing an insulative material including at least one layer of a conformal oxide, the insulative material forming on either side of said uncovered predetermined region of the substrate a boss (16) on the plane upper surface of the device. The height of the boss is less than 1 000 .ANG. and the insulative material can also include planarising oxide.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: February 18, 1997
    Assignee: France Telecom
    Inventors: Maryse Paoli, Pierre Brouquet, Michel Haond
  • Patent number: 5330617
    Abstract: The invention relates to a method for etching an integrated-circuit layer to a fixed depth. The method consists in depositing onto the layer to be etched a protective layer forming a stop layer and then onto the latter a reference layer made of a material compatible with that of the layer to be etched the thickness of the reference layer being proportional to the depth of the etch to be produced. A mask is applied to the reference layer and the etching of this layer is carried out by chemical attack until encountering the stop layer. After removal of the mask and of the stop layer, in the etching zone, the reference layer and the layer of material to be etched 1 are simultaneously subjected to a chemical attack until encountering the stop layer. An etch having the plane dimensions of the etch of the reference layer and a depth proportional to the thickness of the reference layer is thus created. Application to the etching of integrated-circuit layers or to the creation of inverted-T-shaped elements.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: July 19, 1994
    Assignee: France Telecom
    Inventor: Michel Haond
  • Patent number: 5089870
    Abstract: An SOI MOS transistor comprises at least a highly doped lateral stripe (13, 14) of the same conductivity type as the substrate (3). This stripe extends along the edge of the substrate and of the source region (5) and is shorted with the source region through the conductive source layer (11).
    Type: Grant
    Filed: June 7, 1990
    Date of Patent: February 18, 1992
    Assignee: L'Etat Francais represente par le Ministre des Postes, des Telecommunications et de l'Espace (Centre National d'Etudes des Telecommunications)
    Inventor: Michel Haond
  • Patent number: 5023197
    Abstract: A method for manufacturing a MOS transistor formed in a silicon block on insulator with convex rounded up edges, initially consisting in etching the block in a thin layer of silicon on insulator (SOI). In this method etching of the block comprises the following steps: forming at the position where it is desired to obtain the block a mask layer portion (3) having a thickness slightly higher than that of the SOI; depositing a second silicon layer (11) having a predetermined thickness; and anisotropically etching silicon until said insulator is apparent outside the mask layer portion.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: June 11, 1991
    Assignee: French State represented by the Minister of Post, Telecommunications and Space
    Inventors: Michel Haond, Jean Galvier
  • Patent number: 4773964
    Abstract: This process consists of producing in the insulating support a periodic configuration which, in the form of regularly spaced parallel insulating strips, has overhanging and recessed parts, the width of the overhanging parts being smaller than that of the recessed parts; depositing on the complete structure obtained a silicon film; covering the silicon film with an encapsulating material layer; carrying out heat treatment in order to recrystallize the silicon film in monocrystalline form, said treatment consisting of locally melting the silicon film and displacing the melted zone parallel to the insulating strips, the melted zone being in the form of a line perpendicular to said strips, followed by the elimination of the encapsulating material layer.
    Type: Grant
    Filed: April 21, 1986
    Date of Patent: September 27, 1988
    Inventor: Michel Haond