Abstract: There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.

Abstract: A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software.

Abstract: A hybrid encryption scheme for storing data lines in a memory includes identifying data lines determined to be frequently accessed, and encrypting the data lines using a first encryption scheme. The hybrid encryption scheme also includes encrypting data lines determined not to be frequently accessed using a second encryption scheme.

Abstract: Errors on a dynamic random access memory (“DRAM”) having an error correcting decoder (“ECC”) can be detected by the ECC when reading a row of the DRAM. The ECC includes error correcting code logic. If errors are detected that cannot be corrected by the ECC logic, test control logic determines weak cell information for the row, evaluates the errors using the weak cell information, and may correct the errors. The weak cell information may include weak cell locations and failure values.

Abstract: Correction of structured burst errors in data is provided by a system that includes an encoder and is configured for performing a method. The method includes receiving data that includes a plurality of subsets of data. The data is encoded by an encoder using a combination of a first error correcting code and a second error correcting code. The first error correcting code is configured to provide error recovery from a structured burst error in one of the subsets of data, the structured burst error having a length less than a specified maximum length. The second error correcting code is configured to extend the first error correcting code to provide error recovery from the structured burst error in any of the subsets of data. The encoded data is output.

Abstract: A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh.

Abstract: A phase change memory (PCM) cell that includes a first electrode contacting a first layer of material having a first chemical composition. The PCM cell also includes a second layer of material having a second chemical composition and a second electrode contacting the first layer of material or the second layer of material. The PCM cell is configured for receiving at least one electrical current pulse flowing from the first electrode to the second electrode to locally heat a region of the first layer and the second layer to cause at least one of inter-diffusion and liquid mixing of the first layer of material and the second layer of material, resulting in a self-aligned region of phase change material having a chemical composition that is a mixture of the first chemical composition and the second chemical composition.

Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.

Abstract: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.

Abstract: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.

Abstract: Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment.

Abstract: Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation.

Abstract: Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment.

Abstract: Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation.

Abstract: A method and system are provided for implementing enhanced flash storage control using reinforcement learning to provide enhanced performance metrics. A flash controller, such as a Reinforcement Learning (RL) flash controller, is coupled to a flash storage. The flash controller defines a feature set of flash parameters determined by a predefined one of a plurality of optimization metrics. The optimization metric is adapted dynamically based upon system workload and system state. The flash controller employing the feature set including at least one feature responsive to erase operations; computes a current system state responsive to the employed feature set; selects actions at each time step by sensing the computed current system state for performing an action to maximize a long term reward, and moves to another state in the system while obtaining a short-term reward for the performed action.

Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

Abstract: This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data.

Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.

Abstract: Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Abstract: Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.