Patents by Inventor Michiaki Takasaka

Michiaki Takasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9824415
    Abstract: An image processing apparatus for processing image data by a plurality of pipeline-connected processing modules is provided. The apparatus includes a first pipeline processing unit configured to include a plurality of processing modules including a processing module which processes image data for every first size; and a second pipeline processing unit configured to be branched from the first pipeline processing unit and include a plurality of processing modules including a processing module which processes image data for every second size different from the first size. The second pipeline processing unit includes, at a start, a change unit configured to acquire partial image data of the first size from the first pipeline processing unit and change the partial image data of the first size into partial image data of the second size.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: November 21, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Patent number: 9626731
    Abstract: Input amount calculation processing and output amount calculation processing corresponding to each processing module are defined. The input amount calculation processing and the output amount calculation processing are performed in a processing order (a reverse order to the processing order) to obtain a favorable peripheral pixel amount.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 18, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Michiaki Takasaka
  • Patent number: 9237097
    Abstract: In an information processing system in which a plurality of modules are connected to a ring bus, data transfer efficiency is enhanced by deleting an unnecessary packet from the ring bus. This invention relates to an information processing system in which a plurality of modules that execute data processing are connected to a ring bus. More particularly, this invention relates to a ring bus operation technique that allows efficient data transfer by monitoring a flag of a packet, and removing an unnecessary packet from the ring bus.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: January 12, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Publication number: 20150117795
    Abstract: An image processing apparatus for processing image data by a plurality of pipeline-connected processing modules is provided. The apparatus includes a first pipeline processing unit configured to include a plurality of processing modules including a processing module which processes image data for every first size; and a second pipeline processing unit configured to be branched from the first pipeline processing unit and include a plurality of processing modules including a processing module which processes image data for every second size different from the first size. The second pipeline processing unit includes, at a start, a change unit configured to acquire partial image data of the first size from the first pipeline processing unit and change the partial image data of the first size into partial image data of the second size.
    Type: Application
    Filed: January 6, 2015
    Publication date: April 30, 2015
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Patent number: 8948542
    Abstract: An image processing apparatus for processing image data by a plurality of pipeline-connected processing modules is provided. The apparatus includes a first pipeline processing unit configured to include a plurality of processing modules including a processing module which processes image data for every first size; and a second pipeline processing unit configured to be branched from the first pipeline processing unit and include a plurality of processing modules including a processing module which processes image data for every second size different from the first size. The second pipeline processing unit includes, at a start, a change unit configured to acquire partial image data of the first size from the first pipeline processing unit and change the partial image data of the first size into partial image data of the second size.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Publication number: 20140241350
    Abstract: In an information processing system in which a plurality of modules are connected to a ring bus, data transfer efficiency is enhanced by deleting an unnecessary packet from the ring bus. This invention relates to an information processing system in which a plurality of modules that execute data processing are connected to a ring bus. More particularly, this invention relates to a ring bus operation technique that allows efficient data transfer by monitoring a flag of a packet, and removing an unnecessary packet from the ring bus.
    Type: Application
    Filed: May 5, 2014
    Publication date: August 28, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: MICHIAKI TAKASAKA, HISASHI ISHIKAWA
  • Patent number: 8761013
    Abstract: In an information processing system in which a plurality of modules are connected to a ring bus, data transfer efficiency is enhanced by deleting an unnecessary packet from the ring bus. This invention relates to an information processing system in which a plurality of modules that execute data processing are connected to a ring bus. More particularly, this invention relates to a ring bus operation technique that allows efficient data transfer by monitoring a flag of a packet, and removing an unnecessary packet from the ring bus.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: June 24, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Publication number: 20140064640
    Abstract: Input amount calculation processing and output amount calculation processing corresponding to each processing module are defined. The input amount calculation processing and the output amount calculation processing are performed in a processing order (a reverse order to the processing order) to obtain a favorable peripheral pixel amount.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 6, 2014
    Inventor: Michiaki Takasaka
  • Patent number: 8417835
    Abstract: There is provided an apparatus including a plurality of modules. Each module includes a storage unit configured to store a waiting ID and a specific ID of the module, a communication unit configured to transmit and receive packets to and from a bus, and a processing unit configured to process data of a packet which includes a valid flag indicating that the packet is valid, wherein the communication unit takes in data held by a packet which has an ID that coincides with the waiting ID, and stores the processed data in a packet which includes the valid flag indicating invalid and an ID coincident with the specific ID, and transmits the packet.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: April 9, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Patent number: 8325377
    Abstract: An image processing apparatus stores, in a buffer, an image data of c bits in the main scanning direction and y lines in the sub scanning direction, and reads out a pixel data of p bits that configures the image data stored in the buffer. Note that c is a common multiple of m, which is the number of bits in the unit of memory access, and p, which is the number of bits in a single pixel.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: December 4, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Patent number: 8213727
    Abstract: An image encoding apparatus generate encoded data having a fixed length L which is less than or equal to m×n bits and an integral multiple of 32 by m×n pixel block, while resolution information and color information are excellently maintained. For this purpose, a block generation unit inputs image data by m×n pixels. A 2-color extraction unit extracts representative colors C0 and C1 from the input block image data. An identification information detection unit generates m×n items of identification information each identifying each pixel in the block as a pixel approximate to one of the colors C0 and C1. An identification information deletion unit deletes the items of identification information in corresponding positions based on a deletion pattern stored in a deletion pattern memory. A packing unit packs the colors C0, C1 and the identification information after deletion, and outputs the data as encoded data.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: July 3, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenta Hosaki, Hisashi Ishikawa, Michiaki Takasaka
  • Publication number: 20120127531
    Abstract: An image processing apparatus stores, in a buffer, an image data of c bits in the main scanning direction and y lines in the sub scanning direction, and reads out a pixel data of p bits that configures the image data stored in the buffer. Note that c is a common multiple of m, which is the number of bits in the unit of memory access, and p, which is the number of bits in a single pixel.
    Type: Application
    Filed: December 1, 2011
    Publication date: May 24, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Publication number: 20110317938
    Abstract: An image processing apparatus for processing image data by a plurality of pipeline-connected processing modules is provided. The apparatus includes a first pipeline processing unit configured to include a plurality of processing modules including a processing module which processes image data for every first size; and a second pipeline processing unit configured to be branched from the first pipeline processing unit and include a plurality of processing modules including a processing module which processes image data for every second size different from the first size. The second pipeline processing unit includes, at a start, a change unit configured to acquire partial image data of the first size from the first pipeline processing unit and change the partial image data of the first size into partial image data of the second size.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 29, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Patent number: 8085427
    Abstract: An image processing apparatus stores, in a buffer, an image data of c bits in the main scanning direction and y lines in the sub scanning direction, and reads out a pixel data of p bits that configures the image data stored in the buffer, in accordance with the completion of the storage of the image data. Note that c is a common multiple of m, which is the number of bits in the unit of memory access, and p, which is the number of bits in a single pixel. Note further that the number of bits in the unit of memory access m is not itself a multiple of the number of bits in a single pixel p.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: December 27, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Publication number: 20110255547
    Abstract: In an information processing system in which a plurality of modules are connected to a ring bus, data transfer efficiency is enhanced by deleting an unnecessary packet from the ring bus. This invention relates to an information processing system in which a plurality of modules that execute data processing are connected to a ring bus. More particularly, this invention relates to a ring bus operation technique that allows efficient data transfer by monitoring a flag of a packet, and removing an unnecessary packet from the ring bus.
    Type: Application
    Filed: February 17, 2010
    Publication date: October 20, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Patent number: 7933049
    Abstract: This invention relates to an MFP having copy and scanner functions. The MFP in which image data flows from a line sensor to a DRAM via an A/D conversion unit and a reading control unit (RCU) and then from an image processing unit (IPU) to a printer via the DRAM has the following arrangement. Both the RCU and the IPU can execute a shading process. In the CM, the RCU executes the shading process. Then, the image is compressed and stored in the DRAM. In the SM, the RCU does not execute the shading process, and the image is temporarily stored in the DRAM without compression. The IPU reads out image data of each rectangle from the DRAM together with shading data, executes the shading process and various kinds of image processing, and outputs the image data to the DRAM.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: April 26, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akihiro Yoshitani, Hisashi Ishikawa, Norikazu Honda, Hirowo Inoue, Michiaki Takasaka
  • Publication number: 20100262719
    Abstract: There is provided an apparatus including a plurality of modules. Each module includes a storage unit configured to store a waiting ID and a specific ID of the module, a communication unit configured to transmit and receive packets to and from a bus, and a processing unit configured to process data of a packet which includes a valid flag indicating that the packet is valid, wherein the communication unit takes in data held by a packet which has an ID that coincides with the waiting ID, and stores the processed data in a packet which includes the valid flag indicating invalid and an ID coincident with the specific ID, and transmits the packet.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 14, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Publication number: 20080317362
    Abstract: An image encoding apparatus generate encoded data having a fixed length L which is less than or equal to m×n bits and an integral multiple of 32 by m×n pixel block, while resolution information and color information are excellently maintained. For this purpose, a block generation unit inputs image data by m×n pixels. A 2-color extraction unit extracts representative colors C0 and C1 from the input block image data. An identification information detection unit generates m×n items of identification information each identifying each pixel in the block as a pixel approximate to one of the colors C0 and C1. An identification information deletion unit deletes the items of identification information in corresponding positions based on a deletion pattern stored in a deletion pattern memory. A packing unit packs the colors C0, C1 and the identification information after deletion, and outputs the data as encoded data.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kenta Hosaki, Hisashi Ishikawa, Michiaki Takasaka
  • Publication number: 20080186541
    Abstract: An image processing apparatus stores, in a buffer, an image data of c bits in the main scanning direction and y lines in the sub scanning direction, and reads out a pixel data of p bits that configures the image data stored in the buffer, in accordance with the completion of the storage of the image data. Note that c is a common multiple of m, which is the number of bits in the unit of memory access, and p, which is the number of bits in a single pixel. Note further that the number of bits in the unit of memory access m is not itself a multiple of the number of bits in a single pixel p.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 7, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Michiaki Takasaka, Hisashi Ishikawa
  • Publication number: 20080007795
    Abstract: This invention relates to an MFP having copy and scanner functions. The MFP in which image data flows from a line sensor to a DRAM via an A/D conversion unit and a reading control unit (RCU) and then from an image processing unit (IPU) to a printer via the DRAM has the following arrangement. Both the RCU and the IPU can execute a shading process. In the CM, the RCU executes the shading process. Then, the image is compressed and stored in the DRAM. In the SM, the RCU does not execute the shading process, and the image is temporarily stored in the DRAM without compression. The IPU reads out image data of each rectangle from the DRAM together with shading data, executes the shading process and various kinds of image processing, and outputs the image data to the DRAM.
    Type: Application
    Filed: July 5, 2007
    Publication date: January 10, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Akihiro Yoshitani, Hisashi Ishikawa, Norikazu Honda, Hirowo Inoue, Michiaki Takasaka