Abstract: A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region.

Abstract: A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region.

Abstract: There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL and UR, disposed on the upper side of a four-bank structure of banks 0 through 3, and memory array regions DL and DR, disposed on the lower side thereof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 ?m. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.

Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.

Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.

Abstract: The object is the present invention is to provide a semiconductor device including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active in which the transistor is formed). By such composition, stress growing in the active due to the shallow trench isolation is equalized among the transistors and thereby the characteristics of the transistors can be equalized.

Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.

Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.

Abstract: An electronic circuit device has a high-density mount board, on which are disposed a microcomputer, a random access memory, a programmable device which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so as to be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device is simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized is simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

Abstract: There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memeory array regions UL and UR, disposed on the upper side of a four-bank structure of banks 0 through 3, and memory array regions DL and DR, disposed on the lower side therof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 ?m. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.

Abstract: A semiconductor device is provided including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active area in which the transistor is formed). By such composition, stress growing in the active area due to the shallow trench isolation is equalized among the transistors, and, thereby, the characteristics of the transistors can be equalized.

Abstract: The object is the present invention is to provide a semiconductor device including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active in which the transistor is formed). By such composition, stress growing in the active due to the shallow trench isolation is equalized among the transistors and thereby the characteristics of the transistors can be equalized.

Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.

Abstract: The object is the present invention is to provide a semiconductor device including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active in which the transistor is formed). By such composition, stress growing in the active due to the shallow trench isolation is equalized among the transistors and thereby the characteristics of the transistors can be equalized.

Abstract: There is provided a large capacity memory such as a DRAM and an SDRAM in which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL and UR, disposed on the upper side of a four-bank structure of banks 0 through 3, and memory array regions DL and DR, disposed on the lower side thereof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 &mgr;m. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.

Abstract: There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.

Abstract: There is provided a large capacity memory such as a DRAM and an SDRAM in which bonding pads PS and PD are put not at the center but aside between memory array regions UL and UR disposed on the upper side of a four-bank structure of banks 0 through 3 and memory array regions DL and DR disposed on the lower side firstly. Secondly, the disposition of the bonding pads Ps and PD is staggered on the right and left and the right half bonding pads PD are shifted up by about 30 &mgr;m. Only a sense amplifier, a column decoder and a main amplifier which need to be approached to the memory array regions DL and DR are disposed between the bonding pads PS and PD and the lower memory array regions DL and DR and indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.

Abstract: There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.

Abstract: There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.

Abstract: There is provided a large capacity memory such as a DRAM and an SDRAM in which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL and UR, disposed on the upper side of a four-bank structure of banks 0 through 3, and memory array regions DL and DR, disposed on the lower side thereof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 &mgr;m. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.