Patents by Inventor Mihir K. Roy

Mihir K. Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220028790
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Mihir K. Roy, Mathew J. Manusharow
  • Patent number: 11158578
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Mathew J Manusharow
  • Publication number: 20210304952
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 30, 2021
    Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
  • Patent number: 10998120
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
  • Patent number: 10971416
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Publication number: 20200294924
    Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Mihir K. Roy, Stefanie M. Lotz, Wei-Lun Kane Jen
  • Patent number: 10734282
    Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Harold Ryan Chase, Mihir K Roy, Mathew J Manusharow, Mark Hlad
  • Publication number: 20200194300
    Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 18, 2020
    Inventors: Manohar S. KONCHADY, Tao WU, Mihir K. ROY, Wei-Lun K. JEN, Yi LI
  • Patent number: 10672713
    Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Stefanie M Lotz, Wei-Lun Kane Jen
  • Patent number: 10629469
    Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Manohar S. Konchady, Tao Wu, Mihir K. Roy, Wei-Lun K. Jen, Yi Li
  • Publication number: 20200111745
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 9, 2020
    Inventors: Mihir K. Roy, Mathew J. Manusharow
  • Publication number: 20190355636
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Patent number: 10446499
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Mathew J Manusharow
  • Patent number: 10410939
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Patent number: 10312007
    Abstract: A method and device includes a first conductor formed on a first dielectric layer as a partial turn of a coil. A second conductor is formed on a second dielectric layer that covers the first dielectric layer and first conductor, the second conductor forming a partial turn of the coil. A vertical interconnect couples the first and second conductors to form a first full turn of the coil. The interconnect coupling can be enhanced by embedding some selective magnetic materials into the substrate.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Mathew J Manusharow, Harold Ryan Chase
  • Publication number: 20190051447
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
  • Publication number: 20190027405
    Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.
    Type: Application
    Filed: September 25, 2018
    Publication date: January 24, 2019
    Inventors: Harold Ryan Chase, Mihir K. Roy, Mathew J. Manusharow, Mark Hlad
  • Publication number: 20190019755
    Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 17, 2019
    Inventors: Mihir K. Roy, Stefanie M Lotz, Wei-Lun Kane Jen
  • Patent number: 10163557
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
  • Publication number: 20180329240
    Abstract: Embodiments are generally directed to a self-cooled laser integrated device and substrate architecture. An embodiment of a device includes a substrate or printed circuit board (PCB); a component coupled with the substrate or PCB, the component including an cooling agent on at least one side of the component; one or more laser sources, at least a first laser source of the one or more laser sources being implemented to direct laser light onto the cooling agent; and a controller to drive the laser source, wherein the cooling agent provides cooling for the component when the laser light is directed on the engineered cooling agent.
    Type: Application
    Filed: December 26, 2015
    Publication date: November 15, 2018
    Inventors: Vivek RAGHUNATHAN, Mihir K. ROY, Ravindranath V. MAHAJAN