Patents by Inventor Miho Kobayashi

Miho Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210130968
    Abstract: The surface-treated material (10) according to the present invention is a surface-treated material including an electroconductive substrate (1) and a surface treatment coating film (2) including at least one metal layer formed above the electroconductive substrate (1), wherein a lowermost metal layer (21), as a metal layer included in the at least one metal layer and formed above the electroconductive substrate (1), is made of nickel, nickel alloy, cobalt, cobalt alloy, copper, or copper alloy, the surface-treated material includes an intervening layer (3) between the electroconductive substrate (1) and the surface treatment coating film (2), the intervening layer (3) containing a metal component of the electroconductive substrate (1), a metal component of the surface treatment coating film (2), and an oxygen component, and the mean thickness of the intervening layer (3) is in the range of 1.00 nm or larger and 40 nm or smaller as measured in the vertical cross-section of the surface-treated material.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 6, 2021
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Miho YAMAUCHI, Yoshiaki KOBAYASHI
  • Publication number: 20210056530
    Abstract: An application executed at a user terminal with a touch screen displays, on the touch screen, a UI in which a user-side UI for accepting a touch operation by a user and a store-side UI for accepting a touch operation by a staff member of a store are placed, as a settlement UI for settlement of a currency amount of a digital local currency. The application judges whether time during which the touch operation on the user-side UI and the touch operation on the store-side UI are simultaneously continued has reached a specified period of time or not. If the judgment result is true, the application displays a settlement completion notice on the touch screen.
    Type: Application
    Filed: July 6, 2020
    Publication date: February 25, 2021
    Applicant: Hitachi, Ltd.
    Inventors: Toshiomi MORIKI, Yuuichi KUROSAWA, Hiroki SATOH, Miho KOBAYASHI
  • Publication number: 20200356297
    Abstract: Example implementations described herein are directed to systems and methods to manage log data that is stored to a storage system. In example implementations, received log data is classified for storage into a storage system having a high tier storage and a low tier storage. For the classification indicative of storage into the high tier storage of the storage system, the storage system stores the log data into the high tier storage, and moves related log data stored in the low tier storage to the high tier storage. For the classification indicative of storage into the low tier storage of the storage system, the storage system stores the log data into the low tier storage and moves the related log data stored in the high tier storage to the low tier storage.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 12, 2020
    Inventors: Miho KOBAYASHI, Hideo SAITO
  • Patent number: 10783096
    Abstract: A storage system provides a logical volume to a computer, manages the logical volume and a port receiving an I/O request for the logical volume in correspondence with each other, and holds assigned processor management information for managing correspondence between a processor for executing I/O processing based on an I/O request accumulated in a queue and an assigned port being a port corresponding to the queue. The processor identifies an assigned port on the basis of the assigned processor management information, executes I/O processing for the logical volume corresponding to the assigned port, and executes I/O processing on the basis of an I/O request received via the assigned port corresponding to another operation core.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 22, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takashi Nagao, Tomohiro Yoshihara, Kohei Tatara, Miho Kobayashi
  • Publication number: 20190286583
    Abstract: A storage system provides a logical volume to a computer, manages the logical volume and a port receiving an I/O request for the logical volume in correspondence with each other, and holds assigned processor management information for managing correspondence between a processor for executing I/O processing based on an I/O request accumulated in a queue and an assigned port being a port corresponding to the queue. The processor identifies an assigned port on the basis of the assigned processor management information, executes I/O processing for the logical volume corresponding to the assigned port, and executes I/O processing on the basis of an I/O request received via the assigned port corresponding to another operation core.
    Type: Application
    Filed: August 30, 2018
    Publication date: September 19, 2019
    Applicant: HITACHI, LTD.
    Inventors: Takashi Nagao, Tomohiro Yoshihara, Kohei Tatara, Miho Kobayashi
  • Publication number: 20180204387
    Abstract: To arrange an entire peripheral image in the virtual three-dimensional space in an easy-to-grasp manner, it is provided an image generation device, which is configured to generate an image to be displayed on a display device, the image generation device comprising: a processor configured to execute a program; and a memory configured to store the program, wherein the processor is configured to: arrange a three-dimensional model of an object existing in a real space in a virtual three-dimensional space; arrange at least one tube-shaped virtual screen including a predetermined photographing position in the virtual three-dimensional space; execute arithmetic processing of mapping an entire peripheral image captured at the predetermined photographing position to the at least one tube-shaped virtual screen; and generate image data for displaying, in a panoramic view, the virtual three-dimensional space in which the three-dimensional model and the at least one tube-shaped virtual screen are arranged.
    Type: Application
    Filed: July 28, 2015
    Publication date: July 19, 2018
    Inventors: Kei UTSUGI, Miho KOBAYASHI, Koji ARA
  • Patent number: 9619007
    Abstract: An integrated circuit device includes first and second integrated circuits and a power supply line. The first integrated circuit includes a first power supply circuit, a timing generation circuit generating a synchronization signal, and a first power supply control section. The second integrated circuit includes a second power supply circuit and a second power supply control section. The power supply line electrically connects the outputs of the first and second power supply circuit. The first and second power supply control sections are each configured to start the operations of the first and second power supply circuits, respectively, in response to a start of a supply of the synchronization signal after a sleep-out command is supplied thereto. The timing generation circuit starts supplying the synchronization signal after a predetermined waiting time elapses after the sleep-out command is supplied to the first integrated circuit.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: April 11, 2017
    Assignee: SYNAPTICS JAPAN GK
    Inventors: Toshio Mizuno, Miho Kobayashi, Junpei Sakurai
  • Publication number: 20140164806
    Abstract: An integrated circuit device includes first and second integrated circuits and a power supply line. The first integrated circuit includes a first power supply circuit, a timing generation circuit generating a synchronization signal, and a first power supply control section. The second integrated circuit includes a second power supply circuit and a second power supply control section. The power supply line electrically connects the outputs of the first and second power supply circuit. The first and second power supply control sections are each configured to start the operations of the first and second power supply circuits, respectively, in response to a start of a supply of the synchronization signal after a sleep-out command is supplied thereto. The timing generation circuit starts supplying the synchronization signal after a predetermined waiting time elapses after the sleep-out command is supplied to the first integrated circuit.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 12, 2014
    Applicant: Renesas SP Drivers Inc.
    Inventors: Toshio MIZUNO, Miho Kobayashi, Junpei Sakurai
  • Publication number: 20060057281
    Abstract: A method of producing a membrane-electrode assembly for a fuel cell remarkably enhances the productivity and properties of fuel cell. There are provided in the method a first catalyst layer forming step of spreading a first coating compound over a running substrate to form a first catalyst layer, an electrolyte forming step of spreading a second coating compound over said first catalyst layer while the first catalyst layer is wet to form an electrolyte layer, a drying step of drying the electrolyte layer, and a second catalyst layer forming step of spreading a third coating compound having a noble metal supported thereon over the dried electrolyte layer to form a second catalyst layer.
    Type: Application
    Filed: July 28, 2003
    Publication date: March 16, 2006
    Inventors: Shintaro Izumi, Nobuyuki Kamikihara, Masaru Watanabe, Yusuke Ozaki, Miho Kobayashi, Yasuhiro Ueyama
  • Patent number: 5847757
    Abstract: A driving method for a solid-state image sensing device includes the steps of: transferring signal charges generated at pixels (12) arranged in odd rows in the column upward direction through vertical transfer paths (13) each arranged for each column; temporarily accumulating the upward transferred signal charges for one field at a first accumulation region (14) and transferring the accumulated signal charges row by row in sequence for each field period through other vertical transfer paths (18) to a first horizontal path (16); transferring the upward transferred signal charges in the horizontal row direction row by row through the first horizontal transfer path (16); transferring signal charges generated at pixels (12) arranged in even rows in the column downward direction through the same vertical transfer paths (13); temporarily accumulating the downward transferred signal charges for one field at a second accumulation region (15) and transferring the accumulated signal charges row by row in sequence for e
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: December 8, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobusuke Sasano, Kenichi Arakawa, Tomoaki Iizuka, Miho Kobayashi, Hideki Motoyama, Tetsuo Yamada
  • Patent number: 5500675
    Abstract: In the method of driving a solid-state image sensing device, for each vertical blanking (VBL), the signal charges of a first pixel group composed of photosensitive pixels of odd ordinal numbers counted in the vertical direction of the photosensitive region and the signal charges of a second pixel group composed of photosensitive pixels of even ordinal numbers counted in the same way are reversed in the vertical transfer direction, so that the signal charges of the first and second pixel groups can be outputted from the same charge detecting circuit for each field. Further, unnecessary accumulated charges in the pixel groups in the photosensitive region are cleared off in response to an accumulated charge clear pulse.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: March 19, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Arakawa, Nobusuke Sasano, Tomoaki Iizuka, Miho Kobayashi, Tetsuo Yamada, Hideki Motoyama
  • Patent number: 5396091
    Abstract: Solid-state image sensing device is provided with a synthesizing section for synthesizing odd-field signal charges and even-field signal charges. The synthesizing section is a transfer path formed outside of the photosensitive region or vertical transfer paths formed in the photosensitive region. For the signal charge synthesis through vertical transfer path, after the integration, the signal charges are read simultaneously from the odd-line pixel group and the even-line pixel group. Further, it is possible to select either the method of outputting the odd-field signal charges and the even-field signal charges separately or the method of outputting the synthesized odd- and even-field signal charges.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: March 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miho Kobayashi, Tomoaki Iizuka, Hideki Motoyama, Tetsuo Yamada, Kenichi Arakawa, Nobusuke Sasano