Patents by Inventor Miki Moriyama

Miki Moriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230257902
    Abstract: A method for producing a Group III nitride semiconductor includes feeding a nitrogen-containing gas into a molten mixture of a Group III metal and a flux placed in a furnace, to thereby grow a Group III nitride semiconductor on a seed substrate, wherein the Group III nitride semiconductor is grown on the seed substrate, while controlling the surface modification weight ratio, which is defined as the ratio of the weight of Na including a portion surface-modified through oxidation or hydroxidation to the weight of Na when the surface thereof has no surface-modified portion as a reference weight, with Na serving as the flux.
    Type: Application
    Filed: March 20, 2023
    Publication date: August 17, 2023
    Inventors: Takayuki SATO, Miki MORIYAMA, Masateru YAMAZAKI, Taku FUJIMORI
  • Patent number: 11280024
    Abstract: The present invention suppresses anomalous growth of a Group III nitride semiconductor at the periphery of a seed substrate. The invention is directed to a method for producing a Group III nitride semiconductor including feeding a nitrogen-containing gas into a molten mixture of a Group III metal and a flux placed in a furnace, to thereby grow a Group III nitride semiconductor on a seed substrate. The oxygen concentration of the furnace internal atmosphere is elevated after the growth initiation temperature of the Group III nitride semiconductor has been achieved. In a period from the initiation of the growth to a certain timing, the oxygen concentration of the furnace internal atmosphere is controlled to 0.02 ppm or less, and thereafter, to greater than 0.02 ppm and 0.1 ppm or less.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 22, 2022
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takayuki Sato, Miki Moriyama, Shiro Yamazaki, Yasuhide Yakushi
  • Publication number: 20220081800
    Abstract: A method for producing a Group III nitride semiconductor includes feeding a nitrogen-containing gas into a molten mixture of a Group III metal and a flux placed in a furnace, to thereby grow a Group III nitride semiconductor on a seed substrate. At least an oxidation amount of Na, serving as the flux, is controlled outside the furnace, and the controlled Na is fed into the furnace.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Inventors: Takayuki SATO, Miki MORIYAMA, Masateru YAMAZAKI, Taku FUJIMORI
  • Publication number: 20200299857
    Abstract: The present invention suppresses anomalous growth of a Group III nitride semiconductor at the periphery of a seed substrate. The invention is directed to a method for producing a Group III nitride semiconductor including feeding a nitrogen-containing gas into a molten mixture of a Group III metal and a flux placed in a furnace, to thereby grow a Group III nitride semiconductor on a seed substrate. The oxygen concentration of the furnace internal atmosphere is elevated after the growth initiation temperature of the Group III nitride semiconductor has been achieved. In a period from the initiation of the growth to a certain timing, the oxygen concentration of the furnace internal atmosphere is controlled to 0.02 ppm or less, and thereafter, to greater than 0.02 ppm and 0.1 ppm or less.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 24, 2020
    Inventors: Takayuki SATO, Miki MORIYAMA, Masateru YAMAZAKI, Taku FUJIMORI, Shiro YAMAZAKI, Yasuhide YAKUSHI
  • Publication number: 20200299858
    Abstract: The present invention reduces warpage of a Group III nitride semiconductor crystal in a method for producing a Group III nitride semiconductor crystal on a seed substrate through a flux method. A Group III nitride semiconductor is grown so that the total Al amount at the interface is not more than 3×1014/cm2, and the total Si amount at the interface is not more than 5×1014/cm2. Here, the total amount at the interface refers to a total number of atoms per unit area of an interface between the grown Group III nitride semiconductor and the seed substrate. Thus, warpage can be reduced by growing a Group III nitride semiconductor through a flux method.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 24, 2020
    Inventors: Shiro YAMAZAKI, Miki MORIYAMA
  • Patent number: 10693032
    Abstract: The seed substrate comprises a base substrate and a base layer comprising a Group III nitride semiconductor formed on the base substrate, which has a high dislocation density region and a low dislocation density region. The planar pattern of the high dislocation density region is a honeycomb pattern. A hollow exists between the base substrate and the low dislocation density region. The object layer is grown through a flux method using the seed substrate. The high dislocation density region is melted back at an initial stage of crystal growth, and thereafter, the object layer is grown on the top surface of the low dislocation density region. A cavity remains between the high dislocation density region and the object layer. The presence of the cavity and the hollow makes easy to peel the object layer from the seed substrate.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 23, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Miki Moriyama, Shiro Yamazaki, Shohei Kumegawa
  • Patent number: 10329687
    Abstract: To reduce ungrown region or abnormal grain growth region in growing a Group III nitride semiconductor through a flux method. A seed substrate has a structure in which a Group III nitride semiconductor layer is formed on a ground substrate as a base, and a mask is formed on the Group III nitride semiconductor layer. The mask has a plurality of dotted windows in an equilateral triangular lattice pattern. A Group III nitride semiconductor is grown through flux method on the seed substrate. Carbon is placed on a lid of a crucible holing the seed substrate and a molten mixture so that carbon is not contact with the molten mixture at the start of crystal growth. Thereby, carbon is gradually added to the molten mixture as time passes. Thus, ungrown region or abnormal grain growth region is reduced in the Group III nitride semiconductor crystal grown on the seed substrate.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 25, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Miki Moriyama, Shiro Yamazaki, Yasuhide Yakushi
  • Publication number: 20180097142
    Abstract: The seed substrate comprises a base substrate and a base layer comprising a Group III nitride semiconductor formed on the base substrate, which has a high dislocation density region and a low dislocation density region. The planar pattern of the high dislocation density region is a honeycomb pattern. A hollow exists between the base substrate and the low dislocation density region. The object layer is grown through a flux method using the seed substrate. The high dislocation density region is melted back at an initial stage of crystal growth, and thereafter, the object layer is grown on the top surface of the low dislocation density region. A cavity remains between the high dislocation density region and the object layer. The presence of the cavity and the hollow makes easy to peel the object layer from the seed substrate.
    Type: Application
    Filed: September 25, 2017
    Publication date: April 5, 2018
    Inventors: Miki MORIYAMA, Shiro Yamazaki, Shohei Kumegawa
  • Patent number: 9932688
    Abstract: The present techniques provide a method for producing a Group III nitride semiconductor single crystal that is designed to grow a semiconductor single crystal with high reproducibility. The method for producing a Group III nitride semiconductor single crystal comprises adding a seed crystal substrate, Ga, and Na into a crucible, and growing a Group III nitride semiconductor single crystal. In the growth of the Group III nitride semiconductor single crystal, a measuring device is used to detect the reaction of Ga with Na. Ga is reacted with Na with the temperature of the crucible adjusted within a first temperature range of 80° C. to 200° C. After the measuring device detected the reaction of Ga with Na, the temperature of the crucible is elevated up to a growth temperature of the Group III nitride semiconductor single crystal.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: April 3, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Miki Moriyama
  • Publication number: 20180066378
    Abstract: To reduce ungrown region or abnormal grain growth region in growing a Group III nitride semiconductor through a flux method. A seed substrate has a structure in which a Group III nitride semiconductor layer is formed on a ground substrate as a base, and a mask is formed on the Group III nitride semiconductor layer. The mask has a plurality of dotted windows in an equilateral triangular lattice pattern. A Group III nitride semiconductor is grown through flux method on the seed substrate. Carbon is placed on a lid of a crucible holing the seed substrate and a molten mixture so that carbon is not contact with the molten mixture at the start of crystal growth. Thereby, carbon is gradually added to the molten mixture as time passes. Thus, ungrown region or abnormal grain growth region is reduced in the Group III nitride semiconductor crystal grown on the seed substrate.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 8, 2018
    Inventors: Miki MORIYAMA, Shiro YAMAZAKI, Yasuhide YAKUSHI
  • Patent number: 9903042
    Abstract: An object of the present invention is to suppress macro step growth in the growth of GaN crystal through a flux method. As a crucible for holding a melt when growing a GaN crystal through the Na flux method, the crucible is made of alumina and produced by plaster mold casting. The crucible is used, in which there are alumina grains abnormally grown on the inner walls thereof, and the maximum grain size of the abnormally grown alumina grains is not less than 10 ?m. When such a crucible is selected and used, the macro step growth can be suppressed, thereby improving the GaN crystal quality.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: February 27, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Masateru Yamazaki, Miki Moriyama
  • Patent number: 9691610
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor crystal and a GaN substrate, in which the transfer of dislocation density or the occurrence of cracks can be certainly reduced on a growth substrate, and the Group III nitride semiconductor crystal can be easily separated from a seed crystal. A mask layer is formed on a GaN substrate, to thereby form an exposed portion of the GaN substrate, and an unexposed portion of the GaN substrate. Through a flux method, a GaN layer is formed on the exposed portions of the GaN substrate in a molten mixture containing at least Group III metal and Na. At that time, non-crystal portions containing the components of the molten mixture are formed on the mask layer so as to be covered with the GaN layer grown on the GaN substrate and the mask layer.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: June 27, 2017
    Assignee: TOYODA GOSEI CO., LTD
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Publication number: 20170081780
    Abstract: A method for producing a Group III nitride semiconductor single crystal, includes forming a mask layer on an underlayer, to thereby form a seed crystal in which a portion of the underlayer is covered with the mask layer and in which the remaining portion of the underlayer is not covered with the mask layer, etching the remaining portion, and growing a Group III nitride semiconductor single crystal on the seed crystal.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Seiji NAGAI, Miki MORIYAMA, Shohei KUMEGAWA, Shiro YAMAZAKI
  • Publication number: 20170058425
    Abstract: The present techniques provide a method for producing a Group III nitride semiconductor single crystal that is designed to grow a semiconductor single crystal with high reproducibility. The method for producing a Group III nitride semiconductor single crystal comprises adding a seed crystal substrate, Ga, and Na into a crucible, and growing a Group III nitride semiconductor single crystal. In the growth of the Group III nitride semiconductor single crystal, a measuring device is used to detect the reaction of Ga with Na. Ga is reacted with Na with the temperature of the crucible adjusted within a first temperature range of 80° C. to 200° C. After the measuring device detected the reaction of Ga with Na, the temperature of the crucible is elevated up to a growth temperature of the Group III nitride semiconductor single crystal.
    Type: Application
    Filed: August 17, 2016
    Publication date: March 2, 2017
    Inventor: Miki MORIYAMA
  • Patent number: 9567693
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor single crystal having excellent crystallinity, and a method for producing a GaN substrate having excellent crystallinity, the method including controlling melting back. Specifically, a mask layer is formed on a GaN substrate serving as a growth substrate. Then, a plurality of trenches which penetrate the mask layer and reach the GaN substrate are formed through photolithography. The obtained seed crystal and raw materials of a single crystal are fed to a crucible and subjected to treatment under pressurized and high temperature conditions. Portions of the GaN substrate exposed to the trenches undergo melting back with a flux. Through dissolution of the GaN substrate, the dimensions of the trenches increase, to provide large trenches. The GaN layer is grown from the surface of the mask layer as a starting point.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 14, 2017
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Miki Moriyama, Shohei Kumegawa, Shiro Yamazaki
  • Patent number: 9388506
    Abstract: The present invention provides a semiconductor crystal removal apparatus which realizes effective removal of a semiconductor crystal from a crucible through rapid melting of a solidified flux, and a method for producing a semiconductor crystal. The semiconductor crystal removal apparatus includes a crucible support for supporting a crucible so that the opening of the crucible is directed downward; a heater for heating the crucible supported on the crucible support; and a semiconductor crystal receiving net for receiving a semiconductor crystal falling from the opening of the crucible. The semiconductor crystal removal apparatus further includes a determination portion for determining removal of the semiconductor crystal on the basis of a change in weight through falling of the semiconductor crystal.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: July 12, 2016
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Shiro Yamazaki, Seiji Nagai, Miki Moriyama
  • Publication number: 20160160381
    Abstract: An object of the present invention is to suppress macro step growth in the growth of GaN crystal through a flux method. As a crucible for holding a melt when growing a GaN crystal through the Na flux method, the crucible is made of alumina and produced by plaster mold casting. The crucible is used, in which there are alumina grains abnormally grown on the inner walls thereof, and the maximum grain size of the abnormally grown alumina grains is not less than 10 ?m. When such a crucible is selected and used, the macro step growth can be suppressed, thereby improving the GaN crystal quality.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 9, 2016
    Inventors: Masateru YAMAZAKI, Miki Moriyama
  • Patent number: 9315416
    Abstract: A method of manufacturing a light-emitting device including a light-emitting element mounted on a substrate and sealed with a glass. The method includes heating the glass by a first mold that is heated to a temperature higher than a yield point of the glass, the glass contacting the first mold, and pressing the glass against the light-emitting element mounted on the substrate supported by a second mold to seal the light-emitting element with the glass.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: April 19, 2016
    Assignees: TOYODA GOSEI CO., LTD., SUMITA OPTICAL GLASS, INC.
    Inventors: Seiji Yamaguchi, Koji Tasumi, Hiroyuki Tajima, Satoshi Wada, Miki Moriyama, Kazuya Aida, Hiroki Watanabe
  • Patent number: 9153439
    Abstract: A mask layer is formed on a Ga polarity surface of the GaN substrate as a growth substrate. Subsequently, a protective film PF is formed on a N polarity surface of the GaN substrate. Then, a plurality of concave portions is formed from the mask layer extending to the GaN substrate, to thereby form a seed crystal. The seed crystal is etched in a Na melt, and a plurality of concave portions having a facet plane exposed. The seed crystal and the raw materials are placed in a crucible, and the pressure and temperature inside the crucible are increased. Thus, a target GaN layer is grown in the upward direction on the surface of the mask layer and the lateral direction over the concave portions.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: October 6, 2015
    Assignee: Toyoda Gosei Co., Ltd
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Patent number: 9099627
    Abstract: Sample A is produced by sequentially forming a first insulating film of SiO2 and a reflective film on a sapphire substrate. Sample B is produced by sequentially forming a first insulating film of SiO2, a reflective film, and a second insulating film of SiO2 on a sapphire substrate. In both samples A and B, the reflectance of the reflective film was measured at a wavelength of 450 nm before and after heat treatment. Heat treatment was performed at 600° C. for three minutes. As shown in FIG. 1, in Al/Ag/Al where Al has a thickness of 1 ? to 30 ?, Ag/Al where Al has a thickness of 20 ?, and Al/Ag/Al/Ag/Al where Al has a thickness of 20 ?, the reflectance was 95% or more, which is equivalent to or higher than that of Ag even after the heat treatment.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: August 4, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Shingo Totani, Masashi Deguchi, Miki Moriyama