Patents by Inventor Miki Suzuki
Miki Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130284509Abstract: A connection structure includes a column electrode; a first connecting portion connected to one end of the column electrode; and a second connecting portion connected to another end of the column electrode via solder, wherein a height of the column electrode is a width of the first connecting portion or greater.Type: ApplicationFiled: April 22, 2013Publication date: October 31, 2013Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kei Murayama, Shinji Nakazawa, Miki Suzuki
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Publication number: 20130280949Abstract: A connector includes a female connector and a male connector fitted in a hood of the female connector. The female connector includes: paired guide grooves either provided at opposed positions on an inside wall of the hood; and regulation projections either provided on bottom surfaces of the paired guide grooves. The male connector includes paired guide ribs provided on an outer periphery of the male connector. The paired guide ribs either positioned in the paired guide grooves with the female connector and the male connector being fitted together regulate a relative rotational movement between the female and male connector. The regulation projections either in contact with the paired guide ribs regulate a relative vertical and transverse movement between the female and male connectors.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Inventors: Miki SUZUKI, Takashi MATSUNAGA
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Patent number: 8530973Abstract: It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions.Type: GrantFiled: July 12, 2012Date of Patent: September 10, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Miki Suzuki
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Publication number: 20130009247Abstract: It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions.Type: ApplicationFiled: July 12, 2012Publication date: January 10, 2013Inventors: Kazuya Hanaoka, Miki Suzuki
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Patent number: 8222097Abstract: It is an object to form a conductive region between a front surface and a rear surface of an insulating film without forming contact holes in the insulating film.Type: GrantFiled: August 25, 2009Date of Patent: July 17, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Miki Suzuki
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Publication number: 20120153395Abstract: A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction.Type: ApplicationFiled: December 9, 2011Publication date: June 21, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Junichi KOEZUKA, Satoshi SHINOHARA, Miki SUZUKI, Hideto OHNUMA
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Patent number: 7978750Abstract: A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.Type: GrantFiled: June 29, 2005Date of Patent: July 12, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hideo Nunokawa, Miki Suzuki, Hiroyuki Abe, Shinichi Okamoto, Shunichi Ko, Hiroshi Haibara, Nobuhiko Akasaka
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Publication number: 20100055894Abstract: It is an object to form a conductive region between a front surface and a rear surface of an insulating film without forming contact holes in the insulating film.Type: ApplicationFiled: August 25, 2009Publication date: March 4, 2010Inventors: Kazuya Hanaoka, Miki Suzuki
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Patent number: 7554305Abstract: Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.Type: GrantFiled: November 12, 2004Date of Patent: June 30, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Hideo Nunokawa, Tatsuo Kato, Miki Suzuki, Tomonari Morishita
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Publication number: 20060223452Abstract: A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.Type: ApplicationFiled: June 29, 2005Publication date: October 5, 2006Applicant: FUJITSU LIMITEDInventors: Hideo Nunokawa, Miki Suzuki, Hiroyuki Abe, Shinichi Okamoto, Shunichi Ko, Hiroshi Haibara, Nobuhiko Akasaka
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Publication number: 20060012354Abstract: Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.Type: ApplicationFiled: November 12, 2004Publication date: January 19, 2006Inventors: Hideo Nunokawa, Tatsuo Kato, Miki Suzuki, Tomonari Morishita
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Publication number: 20010045873Abstract: The present invention relates to a noise reduction circuit suitably used for an in-vehicle electronic equipment requiring an EMI countermeasure and a semiconductor device including the noise reduction circuit, and has an object to provide a noise reduction circuit which can reduce undesired radiant noise generated from a semiconductor device and a semiconductor device including the noise reduction circuit. An LSI chip 1 includes a power supply terminal 4 for supplying an external power supply voltage to an internal circuit 2 including a circuit operating in synchronization with a clock, and a ground terminal 6 for giving a ground potential.Type: ApplicationFiled: February 1, 2001Publication date: November 29, 2001Inventors: Miki Suzuki, Hideo Nunokawa
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Patent number: 6207151Abstract: Aqueous protein-containing solutions, in which a protein is dissolved at a high concentration at a pH near the isoelectric point of the protein by adding an anionic polymer or a salt thereof to the solution. Pharmaceutical formulations using a physiologically active protein are prepared using this technique.Type: GrantFiled: June 13, 1994Date of Patent: March 27, 2001Assignee: Mitsui Chemicals Inc.Inventors: Yukio Shimazaki, Nobuhiro Kawashima, Miki Suzuki, Yasuhito Tanaka, Ryo Tanaka, Kiyoshi Sakai, Hisahiro Ishiwari
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Patent number: 6063300Abstract: A method of manufacturing a semiconductor device, including the steps of: cooling a semiconductor wafer to a predetermined temperature, the semiconductor wafer being mounted on a stage provided with cooling means and having a thin oxide film on a surface thereof; supplying energy to gas containing hydrogen and water vapor to excite the gas into a plasma state; adding nitrogen fluoride downstream into a flow of the gas in the plasma state; and introducing a flow of the gas, including the nitrogen fluoride, to the semiconductor wafer to etch the thin oxide film while maintaining the semiconductor wafer at the predetermined temperature.Type: GrantFiled: February 20, 1998Date of Patent: May 16, 2000Assignee: Fujitsu LimitedInventors: Miki Suzuki, Jun Kikuchi, Mitsuaki Nagasaka, Shuzo Fujimura
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Patent number: 4875970Abstract: A method of forming, on a surface of a Mn-Zn ferrite single crystal, a recessed portion which has a predetermined cross sectional profile and at least one straight ridge each of which defines a boundary in the profile. An etching mask is formed on the surface of the ferrite single crystal, so as to provide the recessed portion by etching such that each straight edge of the profile lies in a (100) or (110) plane of the ferrite single crystal which is perpendicular to the surface on which the etching mask is formed. The ferrite single crystal with the etching mask in exposed to an aqueous solution which substantially consists of water and the balance consisting principally of phosphoric acid, whereby the surface of the ferrite single crystal is chemically etched, so as to produce the recessed portion such that an inclined surface is formed so as to extend parallel to the straight ridge, and such that the straight ridge defines an edge of the inclined surface.Type: GrantFiled: December 29, 1988Date of Patent: October 24, 1989Assignee: NGK Insulators, Ltd.Inventors: Fuminori Takeya, Naoya Fukuda, Miki Suzuki
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Patent number: D468198Type: GrantFiled: April 23, 2001Date of Patent: January 7, 2003Assignee: Toshiba Battery Co., Ltd.Inventors: Manami Nakazawa, Miki Suzuki, Megumi Nakamura