Patents by Inventor Mikito NOZAKI

Mikito NOZAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11342428
    Abstract: A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: May 24, 2022
    Assignees: Panasonic Holdings Corporation, OSAKA UNIVERSITY
    Inventors: Hong-An Shih, Satoshi Nakazawa, Naohiro Tsurumi, Yoshiharu Anda, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Mikito Nozaki, Takahiro Yamada
  • Publication number: 20200135876
    Abstract: A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.
    Type: Application
    Filed: January 2, 2020
    Publication date: April 30, 2020
    Applicants: Panasonic Corporation, OSAKA UNIVERSITY
    Inventors: Hong-An Shih, Satoshi Nakazawa, Naohiro Tsurumi, Yoshiharu Anda, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Mikito Nozaki, Takahiro Yamada
  • Patent number: 10103232
    Abstract: A semiconductor device (100) includes a base layer (10), an interface layer (20), and a deposition layer (30). The base layer (10) includes a nitride semiconductor that contains gallium. The interface layer (20) is adjacent to the base layer (10). The interface layer (20) contains gallium oxide. The deposition layer (30) is adjacent to the interface layer (20). The deposition layer (30) has a wider band gap than the interface layer (20). The interface layer (20) preferably has crystallinity. The interface layer (20) preferably contains ?-phase Ga2O3.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 16, 2018
    Assignee: OSAKA UNIVERSITY
    Inventors: Heiji Watanabe, Takahiro Yamada, Mikito Nozaki, Takuji Hosoi, Takayoshi Shimura
  • Publication number: 20180061954
    Abstract: A semiconductor device (100) includes a base layer (10), an interface layer (20), and a deposition layer (30). The base layer (10) includes a nitride semiconductor that contains gallium. The interface layer (20) is adjacent to the base layer (10). The interface layer (20) contains gallium oxide. The deposition layer (30) is adjacent to the interface layer (20). The deposition layer (30) has a wider band gap than the interface layer (20). The interface layer (20) preferably has crystallinity. The interface layer (20) preferably contains ?-phase Ga2O3.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 1, 2018
    Applicant: OSAKA UNIVERSITY
    Inventors: Heiji WATANABE, Takahiro YAMADA, Mikito NOZAKI, Takuji HOSOI, Takayoshi SHIMURA