Abstract: A parallel hypervisor system for virtualizing application-specific supercomputers is disclosed. The hypervisor system comprises (a) at least one software-virtual hardware pair consisting of a software application, and an application-specific virtual supercomputer for accelerating the said software application, wherein (i) The virtual supercomputer contains one or more virtual tiles; and (ii) The software application and the virtual tiles communicate among themselves with messages; (b) One or more reconfigurable physical tiles, wherein each virtual tile of each supercomputer can be implemented on at least one physical tile, by configuring the physical tile to perform the virtual tile's function; and (c) A scheduler implemented substantially in hardware, for parallel pre-emptive scheduling of the virtual tiles on the physical tiles.

Abstract: A parallel hypervisor system for virtualizing application-specific supercomputers is disclosed. The hypervisor system comprises (a) at least one software-virtual hardware pair consisting of a software application, and an application-specific virtual supercomputer for accelerating the said software application, wherein (i) The virtual supercomputer contains one or more virtual tiles; and (ii) The software application and the virtual tiles communicate among themselves with messages; (b) One or more reconfigurable physical tiles, wherein each virtual tile of each supercomputer can be implemented on at least one physical tile, by configuring the physical tile to perform the virtual tile's function; and (c) A scheduler implemented substantially in hardware, for parallel pre-emptive scheduling of the virtual tiles on the physical tiles.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method implement value prediction in a data cache miss lookaside buffer that maintains predicted values only for load instructions that miss a data cache. As a result, whenever a load instruction misses a cache, the predicted value therefor may be retrieved from the buffer concurrently with servicing of the cache miss so that subsequent instructions can be speculatively executed while the actual value is retrieved. By limiting the buffer to storing only predicted values for load instructions that miss the data cache, the size of the buffer can be reduced compared to conventional designs, thereby providing more effective value prediction for a given size of buffer.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method reduce the memory access latency of sequences of memory access requests by processing at least one request in a sequence out of order relative to another request based upon whether the other request is likely to be for data maintained in the same organizational block (e.g., a cache line) as data requested by an earlier memory access request in the sequence. Given that multiple requests for data in the same block will collectively hit or miss a given level of memory, whenever a miss occurs as a result of an earlier request, the later requests for data in the same block would otherwise stall until processing of the miss was complete.

Abstract: The data cache management mechanism of the present invention is created by an optimizing compiler. The optimizing compiler intelligently places non-blocking preload instructions into the instruction stream of the computer system so as to minimize both the frequency and detrimental effect of cache misses. The non-blocking preload instructions are placed into the instruction stream based on the existence of predictor constructs that foretell what information the processor will need and when it will need it. As a result, cache misses are either avoided entirely or reduced in severity.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method dispatch multiple copies of a producer instruction to multiple execution units in a processor whenever it is determined that the producer instruction has or is likely to have multiple consumer instructions that are dependent on the producer instruction. Thus, when the multiple consumer instructions are subsequently dispatched to the multiple execution units, the results of the producer instruction are available within those execution units, and without the necessity for any inter-execution unit or inter-microcluster result forwarding. The decision of whether to dispatch multiple copies of a producer instruction may be made at runtime, e.g., within the dispatch unit of a processor, or in the alternative, may be made during compilation of a computer program to be executed on a multi-execution unit processor.

Abstract: A method and apparatus allows a compiler to optimize code in the presence of exception handlers. According to a first embodiment, arcs are added to a control flow graph, prior to performing global optimizations, to account for exception handling code. According to the second embodiment, information relating to control flow to exception handlers is provided in pseudo-references in the code, which allows the compiler to determine how to appropriately optimize the code.

Abstract: Logic for decreasing the number of cache lines dedicated to user data. When pools for allocation are selected using a dynamic storage allocation procedure, the size of a data block is compared to the size of the allocated pool. If the comparison results meet a predetermined criterion, the logic aligns the data to the beginning of a cache line and places the header in a separate cache line that may be deallocated. And if the data will fit within one-half of a cache slot in the allocated pool, then the line or lines having the header data can be re-used as the header is deallocated. Otherwise, user data blocks are placed in cache lines that are spatially local.