Abstract: An ionizing system includes a flange device for connection to a mass spectrometer or ion mobility spectrometer having the property of providing a barrier between the lower pressure region of the spectrometer and a higher pressure region substantially at atmospheric pressure, and a channel therethrough providing fluid communication between the higher and lower pressure regions. A plate device independent of the flange device which can accommodate multiple samples, such as a sample plate device, when placed over the channel in the flange device substantially seals the channel Sliding the sample plate device while in intimate contact with the flange device provides a means to sequentially and rapidly expose said samples to the opening of the channel and thus the lower pressure region. Samples are ionized when exposed to the lower pressure region in as little as one sample per second using multiple ionization methods.

Abstract: A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.

Abstract: A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.

Abstract: A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.

Abstract: A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.

Abstract: A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.

Abstract: A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa.

Abstract: A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.

Abstract: A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.

Abstract: A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa.

Abstract: A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.

Abstract: A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.

Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

Abstract: A semiconductor device includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A flash layer is disposed on the second active layer and source, gate and drain contacts are disposed on the flash layer.

Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

Abstract: A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.

Abstract: A repeatable and uniform low doped layer is formed using modulation doping by forming alternating sub-layers of doped and undoped nitride semiconductor material atop another layer. A Schottky diode is formed of such a low doped nitride semiconductor layer disposed atop a much more highly doped nitride semiconductor layer. The resulting device has both a low on-resistance when the device is forward biased and a high breakdown voltage when the device is reverse biased.

Abstract: A guard ring is formed in a semiconductor region that is part of a Schottky junction or Schottky diode. The guard ring is formed by ion implantation into the semiconductor contact layer without completely annealing the semiconductor contact layer to form a high resistance region. The guard ring may be located at the edge of the layer or, alternatively, at a distance away from the edge of the layer. A Schottky metal contact is formed atop the layer, and the edges of the Schottky contact are disposed atop the guard ring.