Abstract: An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.

Abstract: An establishing method for the timing model includes: identifying at least one first victim path which is a boundary path in a circuit block; determining whether to remove a first aggressor path corresponding to the first victim path according to a transmission delay on the first victim path; finding a plurality of high-fanout circuit devices with a fanout number greater than a preset value in the circuit block; determining whether to remove each of the high-fanout circuit devices according to a connection position of each of the high-fanout circuit devices; identifying a plurality of second victim paths corresponding to each of the high-fanout circuit devices, and determining whether to keep or remove a second aggressor path corresponding to each of the second victim paths according to a transmission delay of each of the second victim paths.

Abstract: An optical element driving mechanism has an optical axis and includes a fixed portion, a movable portion, and a driving assembly. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The driving assembly moves in a first direction to move the movable portion in a second direction, wherein the first direction is different from the second direction.

Abstract: The present disclosure provides an optical element driving mechanism, which includes a movable assembly, a fixed assembly, and a driving assembly. The movable assembly is configured to be connected to an optical element. The movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly in a range of motion. The optical element driving mechanism further includes a positioning assembly configured to position the movable assembly at a predetermined position relative to the fixed assembly when the driving assembly is not operating.

Abstract: An optical system is provided. The optical system includes a first optical module and a second optical module. The first optical module is used for connected to a first optical element. The second optical module is used for connected to a second optical element. A light enters the first optical module along an incident direction, and the light is adjusted by the first optical module to enter the second optical module along a first direction. The incident direction is not parallel with the first direction.

Abstract: An optical element driving mechanism has an optical axis and includes a fixed portion, a movable portion, and a driving assembly. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion, wherein the driving assembly moves along a first direction to move the movable portion along a second direction, the first direction is different from the second direction.

Abstract: An optical system is provided. The optical system includes a first optical module. The first optical module includes a first fixed portion, a first movable portion, a first driving assembly, and a circuit assembly. The first movable portion is used for connecting to a first optical element, and the first movable portion is movably connected to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the first fixed portion. The circuit assembly is electrically connected to the first driving assembly.

Abstract: A method for increasing coverage of a scan test, executed by at least one processor, includes following operations: analyzing a first netlist file and a second netlist file to acquire a change of a circuit structure, in which the first netlist file corresponds to a first scan chain circuitry, and the second netlist file corresponds to a second scan circuitry wherein the second netlist file is generated by processing the first netlist file with executing an engineering change order (ECO); repairing the second scan chain circuitry according to at least one predetermined criterion; evaluating a candidate node of the repaired second scan chain circuitry, to connect a new flip flop circuit generated after executing the ECO to the candidate node; and storing the second netlist file being processed as a third netlist file, to fabricate an integrated circuit.

Abstract: An optical system is provided. The optical system includes a first optical module. The first optical module includes a fixed portion, a movable portion, a driving assembly, and a circuit assembly. The movable portion is movably connected to the fixed portion, and the movable portion is used to connect to an optical element. The driving assembly is used to drive the movable portion to move relative to the fixed portion. The circuit assembly is electrically connected to the driving assembly.

Abstract: A method for increasing coverage of a scan test, executed by at least one processor, includes following operations: analyzing a first netlist file and a second netlist file to acquire a change of a circuit structure, in which the first netlist file corresponds to a first scan chain circuitry, and the second netlist file corresponds to a second scan circuitry wherein the second netlist file is generated by processing the first netlist file with executing an engineering change order (ECO); repairing the second scan chain circuitry according to at least one predetermined criterion; evaluating a candidate node of the repaired second scan chain circuitry, to connect a new flip flop circuit generated after executing the ECO to the candidate node; and storing the second netlist file being processed as a third netlist file, to fabricate an integrated circuit.

Abstract: A timing model building method, for building a timing model corresponding to a gate-level netlist of a block, includes the following operations: utilizing a processor to generate an interface net of the gate-level netlist, where if the gate-level netlist comprises an unconstrained clock tree and boundary timing constraint information of the gate-level netlist does not comprise a timing constraint of the unconstrained clock tree, the interface net comprises none of cells of the gate-level netlist driven by the unconstrained clock tree; utilizing the processor to generate an identified internal net of the gate-level netlist, where the identified internal net is cross-coupled to the interface net; and utilizing the processor to generate the timing model according to the interface net and the identified internal net.

Abstract: A timing model building method, for building a timing model corresponding to a gate-level netlist of a block, includes the following operations: utilizing a processor to generate an interface net of the gate-level netlist, where if the gate-level netlist comprises an unconstrained clock tree and boundary timing constraint information of the gate-level netlist does not comprise a timing constraint of the unconstrained clock tree, the interface net comprises none of cells of the gate-level netlist driven by the unconstrained clock tree; utilizing the processor to generate an identified internal net of the gate-level netlist, where the identified internal net is cross-coupled to the interface net; and utilizing the processor to generate the timing model according to the interface net and the identified internal net.

Abstract: A driving mechanism is provided, including a fixed part, a movable part for holding an optical element, and a driving assembly. The movable part is movable relative to the fixed part and has a first resonance frequency with respect to the fixed part. The driving assembly is configured to drive the movable part to rotate back and forth within a range relative to the fixed part.

Abstract: A driving mechanism is provided, including a fixed part, a movable part for holding an optical element, a driving assembly, and a positioning structure. The movable part is connected to the fixed part. The driving assembly is configured to drive the movable part to move relative to the fixed part. The positioning structure is formed on the movable part or the fixed part for positioning the optical element or at least one part of the driving assembly.

Abstract: A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.

Abstract: A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.

Abstract: A model-building method and a model-building system for executing the method are disclosed. The method includes the following steps: reading a first netlist; extracting a netlist between an input and an initial-stage clock multi-vibrator and extracting a netlist between a final-stage clock multi-vibrator and an output from the first netlist; extracting a netlist between the input and the output from the first netlist; extracting a netlist between a first clock multi-vibrator and a second clock multi-vibrator from the first netlist; extracting netlists between the first clock input and the initial-stage clock multi-vibrator and the first clock multi-vibrator from the first netlist; extracting netlists between the second clock input and the final-stage clock multi-vibrator and the second clock multi-vibrator from the first netlist; and generating a second netlist based on extracted netlists.

Abstract: A model-building method and a model-building system for executing the method are disclosed. The method includes the following steps: reading a first netlist; extracting a netlist between an input and an initial-stage clock multi-vibrator and extracting a netlist between a final-stage clock multi-vibrator and an output from the first netlist; extracting a netlist between the input and the output from the first netlist; extracting a netlist between a first clock multi-vibrator and a second clock multi-vibrator from the first netlist; extracting netlists between the first clock input and the initial-stage clock multi-vibrator and the first clock multi-vibrator from the first netlist; extracting netlists between the second clock input and the final-stage clock multi-vibrator and the second clock multi-vibrator from the first netlist; and generating a second netlist based on extracted netlists.

Abstract: A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.

Abstract: A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.