Patents by Inventor Min-Lung Huang

Min-Lung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210118812
    Abstract: A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Syu-Tang LIU, Min Lung HUANG, Huang-Hsien CHANG, Tsung-Tang TSAI, Ching-Ju CHEN
  • Publication number: 20210074669
    Abstract: A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shun-Tsat TU, Pei-Jen LO, Fong Ren SIE, Cheng-En WENG, Min Lung HUANG
  • Publication number: 20210068267
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Min Lung HUANG
  • Patent number: 10939561
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Min Lung Huang
  • Publication number: 20210035899
    Abstract: A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Min Lung HUANG, Hung-Jung TU, Hsin Hsiang WANG
  • Publication number: 20210020597
    Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Wei CHANG, Shang-Wei YEH, Chung-Hsi WU, Min Lung HUANG
  • Publication number: 20200381375
    Abstract: A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on a first surface of the dielectric layer facing away from the support layer.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Min Lung HUANG, Yuh-Shan SU
  • Publication number: 20200343336
    Abstract: The subject application relates to a semiconductor package device, which includes a first conductive layer; a semiconductor wall disposed on the first conductive layer; a first conductive wall disposed on the first conductive layer; and an insulation layer disposed on the first conductive layer and between the semiconductor wall and the first conductive wall.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao Hsuan CHUANG, Huang-Hsien CHANG, Min Lung HUANG, Yu Cheng CHEN, Syu-Tang LIU
  • Publication number: 20200271942
    Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Feng CHIANG, Tsung-Tang TSAI, Min Lung HUANG
  • Patent number: 10663746
    Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 26, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Feng Chiang, Tsung-Tang Tsai, Min Lung Huang
  • Patent number: 10566279
    Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: February 18, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Jen-Kuang Fang, Min Lung Huang, Chan Wen Liu, Ching Kuo Hsu
  • Patent number: 10388598
    Abstract: A semiconductor process includes: (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space; and (c) forming a redistribution layer on the metal layer, wherein the redistribution layer is electrically connected to the at least one metal via.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: August 20, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Min Lung Huang
  • Publication number: 20190229054
    Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Jen-Kuang FANG, Min Lung HUANG, Chan Wen LIU, Ching Kuo HSU
  • Publication number: 20180129062
    Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.
    Type: Application
    Filed: November 9, 2016
    Publication date: May 10, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Feng CHIANG, Tsung-Tang TSAI, Min Lung HUANG
  • Patent number: 9960102
    Abstract: A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component includes a first substrate, and a first bonding pad disposed adjacent to a first surface of the first substrate, and at least one conductive via structure extending from a second surface of the first substrate to the first bonding pad. The second semiconductor component includes a second substrate, a redistribution layer disposed adjacent to a first surface of the second substrate, and a second bonding pad disposed on the redistribution layer. The connecting element is disposed between the first bonding pad and the second bonding pad.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: May 1, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung-Hsi Wu, Min Lung Huang
  • Patent number: 9960121
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 1, 2018
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Publication number: 20180076122
    Abstract: A semiconductor process includes: (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space; and (c) forming a redistribution layer on the metal layer, wherein the redistribution layer is electrically connected to the at least one metal via.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Min Lung HUANG
  • Patent number: 9852971
    Abstract: An interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via and an isolation material. The metal layer defines at least one through hole having a side wall. The at least one metal via is disposed in the through hole. A space is defined between the at least one metal via and the side wall of the through hole, and the isolation material fills the space. The redistribution layer is disposed on a surface of the interconnection structure and is electrically connected to the metal via.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: December 26, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Min Lung Huang
  • Publication number: 20170358527
    Abstract: An interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via and an isolation material. The metal layer defines at least one through hole having a side wall. The at least one metal via is disposed in the through hole. A space is defined between the at least one metal via and the side wall of the through hole, and the isolation material fills the space. The redistribution layer is disposed on a surface of the interconnection structure and is electrically connected to the metal via.
    Type: Application
    Filed: June 9, 2016
    Publication date: December 14, 2017
    Inventors: Wen-Long LU, Min Lung HUANG
  • Publication number: 20170358518
    Abstract: A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component includes a first substrate, and a first bonding pad disposed adjacent to a first surface of the first substrate, and at least one conductive via structure extending from a second surface of the first substrate to the first bonding pad. The second semiconductor component includes a second substrate, a redistribution layer disposed adjacent to a first surface of the second substrate, and a second bonding pad disposed on the redistribution layer. The connecting element is disposed between the first bonding pad and the second bonding pad.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Chung-Hsi WU, Min Lung HUANG