Patents by Inventor Min-Lung Huang

Min-Lung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190279484
    Abstract: Examples herein disclose an apparatus. The apparatus includes a network interface controller (NIC) port to be dedicated to a management functionality of a server. The apparatus also includes a light emitting diode (LED), coupled to the NIC port, to provide a visible indication that the NIC port is dedicated to the management functionality of the server.
    Type: Application
    Filed: May 14, 2019
    Publication date: September 12, 2019
    Inventors: Min-Lung Ke, Peter Liao, Chun-Hua Huang, Chih-Chieh Wang, Yi-Hsun Chen
  • Patent number: 10388598
    Abstract: A semiconductor process includes: (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space; and (c) forming a redistribution layer on the metal layer, wherein the redistribution layer is electrically connected to the at least one metal via.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: August 20, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Min Lung Huang
  • Publication number: 20190229054
    Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Jen-Kuang FANG, Min Lung HUANG, Chan Wen LIU, Ching Kuo HSU
  • Patent number: 10319211
    Abstract: Examples herein disclose an apparatus. The apparatus includes a network interface controller (NIC) port to be dedicated to a management functionality of a server. The apparatus also includes a light emitting diode (LED), coupled to the NIC port, to provide a visible indication that the NIC port is dedicated to the management functionality of the server.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: June 11, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Min-Lung Ke, Peter Liao, Chun-Hua Huang, Chih-Chieh Wang, Yi-Hsun Chen
  • Publication number: 20180129062
    Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.
    Type: Application
    Filed: November 9, 2016
    Publication date: May 10, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Feng CHIANG, Tsung-Tang TSAI, Min Lung HUANG
  • Patent number: 9960102
    Abstract: A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component includes a first substrate, and a first bonding pad disposed adjacent to a first surface of the first substrate, and at least one conductive via structure extending from a second surface of the first substrate to the first bonding pad. The second semiconductor component includes a second substrate, a redistribution layer disposed adjacent to a first surface of the second substrate, and a second bonding pad disposed on the redistribution layer. The connecting element is disposed between the first bonding pad and the second bonding pad.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: May 1, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung-Hsi Wu, Min Lung Huang
  • Patent number: 9960121
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 1, 2018
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Publication number: 20180076122
    Abstract: A semiconductor process includes: (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space; and (c) forming a redistribution layer on the metal layer, wherein the redistribution layer is electrically connected to the at least one metal via.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Min Lung HUANG
  • Patent number: 9852971
    Abstract: An interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via and an isolation material. The metal layer defines at least one through hole having a side wall. The at least one metal via is disposed in the through hole. A space is defined between the at least one metal via and the side wall of the through hole, and the isolation material fills the space. The redistribution layer is disposed on a surface of the interconnection structure and is electrically connected to the metal via.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: December 26, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Min Lung Huang
  • Publication number: 20170358518
    Abstract: A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component includes a first substrate, and a first bonding pad disposed adjacent to a first surface of the first substrate, and at least one conductive via structure extending from a second surface of the first substrate to the first bonding pad. The second semiconductor component includes a second substrate, a redistribution layer disposed adjacent to a first surface of the second substrate, and a second bonding pad disposed on the redistribution layer. The connecting element is disposed between the first bonding pad and the second bonding pad.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Chung-Hsi WU, Min Lung HUANG
  • Publication number: 20170358527
    Abstract: An interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via and an isolation material. The metal layer defines at least one through hole having a side wall. The at least one metal via is disposed in the through hole. A space is defined between the at least one metal via and the side wall of the through hole, and the isolation material fills the space. The redistribution layer is disposed on a surface of the interconnection structure and is electrically connected to the metal via.
    Type: Application
    Filed: June 9, 2016
    Publication date: December 14, 2017
    Inventors: Wen-Long LU, Min Lung HUANG
  • Publication number: 20160315052
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Application
    Filed: July 5, 2016
    Publication date: October 27, 2016
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Patent number: 9406552
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 2, 2016
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Publication number: 20140175663
    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Jen Chen, Yi-Chuan Ding, Min-Lung Huang
  • Patent number: 8358001
    Abstract: Described herein are semiconductor device packages and redistribution structures including alignment marks and manufacturing methods thereof.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: January 22, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Jen Yang, Chuehan Hsieh, Min-Lung Huang
  • Patent number: 8288853
    Abstract: A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: October 16, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
  • Patent number: 8193647
    Abstract: A semiconductor device package includes a semiconductor device, a sealant, a first dielectric layer, an electrically conductive layer, and a second dielectric layer. The semiconductor device includes a contact pad, an active surface, and side surfaces, where the contact pad is disposed adjacent to the active surface. The semiconductor device is formed with a first alignment mark that is disposed adjacent to the active surface. The sealant envelopes the side surfaces of the semiconductor device and exposes the contact pad. The first dielectric layer is disposed adjacent to the sealant and the active surface, and defines a first aperture that exposes the contact pad. The electrically conductive layer is disposed adjacent to the first dielectric layer and is electrically connected to the contact pad through the first aperture. The second dielectric layer is disposed adjacent to the electrically conductive layer.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: June 5, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chuehan Hsieh, Hung-Jen Yang, Min-Lung Huang
  • Publication number: 20110018118
    Abstract: Described herein are semiconductor device packages and redistribution structures including alignment marks and manufacturing methods thereof.
    Type: Application
    Filed: January 6, 2010
    Publication date: January 27, 2011
    Inventors: Chuehan Hsieh, Hung-Jen Yang, Min-Lung Huang
  • Publication number: 20110018124
    Abstract: Described herein are semiconductor device packages and redistribution structures including alignment marks and manufacturing methods thereof.
    Type: Application
    Filed: December 29, 2009
    Publication date: January 27, 2011
    Inventors: Hung-Jen Yang, Chuehan Hsieh, Min-Lung Huang
  • Publication number: 20100314746
    Abstract: A semiconductor package and a manufacturing method thereof are provided. A carrier having an adhesion layer is provided. A plurality of chips are disposed on the adhesion layer, wherein an active surface of each chip faces the adhesion layer. A molding compound is formed for encapsulating the chips to form a chip-redistribution encapsulant having a first surface and a second surface, wherein the first surface has a chip area and a peripheral area. The carrier and the adhesion layer are removed, so that the chip-redistribution encapsulant exposes the active surface of each chip. A plurality of solder balls are uniformly formed in the chip area and the peripheral area. The second surface of the chip-redistribution encapsulant is grinded to reduce the thickness of the chip-redistribution encapsulant, wherein the solder balls provide the chip-redistribution encapsulant with a uniform support. The chip-redistribution encapsulant is sawn to form a plurality of packages.
    Type: Application
    Filed: October 16, 2009
    Publication date: December 16, 2010
    Inventors: Chueh-An Hsieh, Min-Lung Huang