Patents by Inventor Min-Teng Chen
Min-Teng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12219751Abstract: A semiconductor memory device includes a substrate and a capacitor. The capacitor is disposed on the substrate, and the capacitor includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer sequentially stacked from bottom to top and an aluminum-containing insulation layer. The aluminum-containing insulation layer includes aluminum titanium nitride or aluminum oxynitride, and is in direct contact with the capacitor dielectric layer and disposed between the bottom electrode layer and the top electrode layer. Therefore, the semiconductor memory device may effectively improve the leakage current.Type: GrantFiled: February 17, 2022Date of Patent: February 4, 2025Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventor: Min-Teng Chen
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Patent number: 12016174Abstract: A semiconductor device includes a substrate, a plurality of bit lines, a plurality of contacts, a plurality of storage node pads, a capacitor structure and a plurality of first interface layers. The bit lines and the contacts are disposed on the substrate, and the contacts are alternately and separately disposed with the bit lines. The storage node pads are disposed on the contacts and the bit lines, and are respectively aligned with the contacts. The capacitor structure is disposed on the storage node pads. The first interface layers are disposed between the storage node pads and the capacitor structure, and the first interface layers include a metal nitride material. The first interface layers may improve the granular size of the storage node pads, and reduce the surface roughness thereof, and further improve the electrical connection between the storage nodes and transistor components below.Type: GrantFiled: February 17, 2022Date of Patent: June 18, 2024Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventor: Min-Teng Chen
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Publication number: 20240194594Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and the semiconductor device includes a substrate, a plurality of conductive pads, and a plurality of conductive columns. The conductive pads are separately disposed in a first insulating layer, over the substrate. The conductive columns are separately disposed in a second insulating layer, individually contacting each of the conductive pads. The second insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked on sidewalls of the conductive columns, wherein the second dielectric layer physically contacts the first dielectric layer, the conductive pads and the third dielectric layer at the same time. The second insulating layer is allowable to avoid the short-circuit issue caused by excessively lateral etching, thereby improving the structural reliability and the performances.Type: ApplicationFiled: June 25, 2023Publication date: June 13, 2024Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventor: Min-Teng Chen
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Patent number: 11881503Abstract: The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.Type: GrantFiled: December 9, 2022Date of Patent: January 23, 2024Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen
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Publication number: 20230106501Abstract: The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.Type: ApplicationFiled: December 9, 2022Publication date: April 6, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen
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Publication number: 20230073903Abstract: A semiconductor memory device includes a substrate and a capacitor. The capacitor is disposed on the substrate, and the capacitor includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer sequentially stacked from bottom to top and an aluminum-containing insulation layer. The aluminum-containing insulation layer includes aluminum titanium nitride or aluminum oxynitride, and is in direct contact with the capacitor dielectric layer and disposed between the bottom electrode layer and the top electrode layer. Therefore, the semiconductor memory device may effectively improve the leakage current.Type: ApplicationFiled: February 17, 2022Publication date: March 9, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventor: Min-Teng Chen
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Publication number: 20230070343Abstract: A semiconductor device includes a substrate, a plurality of bit lines, a plurality of contacts, a plurality of storage node pads, a capacitor structure and a plurality of first interface layers. The bit lines and the contacts are disposed on the substrate, and the contacts are alternately and separately disposed with the bit lines. The storage node pads are disposed on the contacts and the bit lines, and are respectively aligned with the contacts. The capacitor structure is disposed on the storage node pads. The first interface layers are disposed between the storage node pads and the capacitor structure, and the first interface layers include a metal nitride material. The first interface layers may improve the granular size of the storage node pads, and reduce the surface roughness thereof, and further improve the electrical connection between the storage nodes and transistor components below.Type: ApplicationFiled: February 17, 2022Publication date: March 9, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventor: Min-Teng Chen
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Patent number: 11557645Abstract: The present invention provides a semiconductor memory device and a fabricating method thereof. The semiconductor memory device includes a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.Type: GrantFiled: April 16, 2021Date of Patent: January 17, 2023Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen
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Publication number: 20220208959Abstract: The present invention provides a semiconductor memory device and a fabricating method thereof. The semiconductor memory device includes a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.Type: ApplicationFiled: April 16, 2021Publication date: June 30, 2022Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen