Patents by Inventor Min Teng

Min Teng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220208959
    Abstract: The present invention provides a semiconductor memory device and a fabricating method thereof. The semiconductor memory device includes a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.
    Type: Application
    Filed: April 16, 2021
    Publication date: June 30, 2022
    Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen
  • Publication number: 20220089613
    Abstract: The present invention relates to compounds and pharmaceutically acceptable salts of Formulas A and B: wherein A, B, R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10 are as defined above. The invention further relates to pharmaceutical compositions comprising the compounds and pharmaceutically acceptable salts and to methods of treating diabetes mellitus and its complications, cancer, ischemia, inflammation, central nervous system disorders, cardiovascular disease, Alzheimer's disease and dermatological disase pression, virus diseases, inflammatory disorders, or diseases in which the liver is a target organ.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Inventors: Hui LI, Seiji NUKUI, Stephanie Anne SCALES, Min TENG, Chunfeng YIN
  • Publication number: 20220081421
    Abstract: Provided herein are heterocyclic derivative compounds and pharmaceutical compositions comprising said compounds that are useful for inhibiting the growth of gram-negative bacteria. Furthermore, the subject compounds and compositions are useful for the treatment of bacterial infection, such as urinary tract infection and the like.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 17, 2022
    Inventors: Min TENG, Baskar NAMMALWAR, Xiaoming LI, Ian YULE, Alastair PARKES, Heather TYE, Holly ATTON, Helen WILLIAMS, Adele FAULKNER, Serge CONVERS-REIGNIER, David T. PUERTA
  • Patent number: 11220518
    Abstract: The present invention relates to compounds and pharmaceutically acceptable salts of Formulas A and B: wherein A, B, R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10 are as defined above. The invention further relates to pharmaceutical compositions comprising the compounds and pharmaceutically acceptable salts and to methods of treating diabetes mellitus and its complications, cancer, ischemia, inflammation, central nervous system disorders, cardiovascular disease, Alzheimer's disease and dermatological disease pression, virus diseases, inflammatory disorders, or diseases in which the liver is a target organ.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: January 11, 2022
    Assignee: PFIZER INC.
    Inventors: Hui Li, Seiji Nukui, Stephanie Anne Scales, Min Teng, Chunfeng Yin
  • Patent number: 11183226
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Publication number: 20210315902
    Abstract: Provided herein is an LpxC inhibitor compound, as well as pharmaceutical compositions comprising said compound, and methods of use thereof in the treatment of disease that would benefit from treatment with an LpxC inhibitor, including gram-negative bacterial infections such as urinary tract infections and the like.
    Type: Application
    Filed: March 24, 2021
    Publication date: October 14, 2021
    Inventors: Min TENG, Baskar NAMMALWAR, David T. PUERTA
  • Publication number: 20210309651
    Abstract: Provided herein is an LpxC inhibitor compound, as well as methods of making and pharmaceutical compositions comprising said compound, and methods of use thereof in the treatment of disease that would benefit from treatment with an LpxC inhibitor, including gram-negative bacterial infections such as urinary tract infections and the like.
    Type: Application
    Filed: March 24, 2021
    Publication date: October 7, 2021
    Inventors: Min TENG, Baskar NAMMALWAR, David T. PUERTA
  • Publication number: 20210221796
    Abstract: Provided herein are heterocyclic derivative compounds and pharmaceutical compositions comprising said compounds that are useful for inhibiting the growth of gram-negative bacteria. Furthermore, the subject compounds and compositions are useful for the treatment of bacterial infection, such as urinary tract infection and the like.
    Type: Application
    Filed: March 18, 2021
    Publication date: July 22, 2021
    Inventors: Min TENG, Baskar NAMMALWAR, Xiaoming LI, Christian PEREZ, Ian YULE, Adele FAULKNER, Holly ATTON, Alastair PARKES, Serge CONVERS-REIGNIER, Michelle SOUTHEY, David T. PUERTA
  • Patent number: 11037607
    Abstract: Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Raymond Chong, Bee Min Teng, Christopher Mozak
  • Patent number: 11021471
    Abstract: Provided herein are heterocyclic derivative compounds and pharmaceutical compositions comprising said compounds that are useful for inhibiting the growth of gram-negative bacteria. Furthermore, the subject compounds and compositions are useful for the treatment of bacterial infection, such as urinary tract infection and the like.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: June 1, 2021
    Assignee: FORGE THERAPEUTICS, INC.
    Inventors: Min Teng, Baskar Nammalwar, Konstantin Taganov, Xiaoming Li, David T. Puerta
  • Publication number: 20210082481
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Publication number: 20210078957
    Abstract: The present teachings relate to hydroxypyridinone and hydroxypyrimidinone derivatives, pharmaceutical compositions thereof, and methods of using such compounds to treat bacterial infections.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Inventors: Min TENG, Baskar NAMMALWAR, Konstantin TAGANOV, David T. PUERTA
  • Patent number: 10875832
    Abstract: The present teachings relate to hydroxypyrimidinone derivatives of Formula II, pharmaceutical compositions thereof, and methods of using such compounds to treat bacterial infections.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 29, 2020
    Assignee: FORGE THERAPEUTICS, INC.
    Inventors: Min Teng, Baskar Nammalwar, Konstantin Taganov, David T. Puerta
  • Patent number: 10865216
    Abstract: Disclosed herein are compounds having the structure of Formula I and pharmaceutically suitable salts, esters, and prodrugs thereof that are useful as antibacterially effective tricyclic gyrase inhibitors. In addition, species of tricyclic gyrase inhibitors compounds are also disclosed herein. Related pharmaceutical compositions, uses and methods of making the compounds are also contemplated.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: December 15, 2020
    Assignees: MERCK SHARP & DOHME CORP., LAWRENCE LIVERMORE NATIONAL SECURITY, LLC
    Inventors: Daniel Bensen, Allen Borchardt, Zhiyong Chen, John M. Finn, Thanh To Lam, Suk Joong Lee, Xiaoming Li, Leslie William Tari, Min Teng, Michael Trzoss, Junhu Zhang, Michael E. Jung, Felice C. Lightstone, Sergio E. Wong, Toan B. Nguyen
  • Patent number: 10854249
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Patent number: 10838282
    Abstract: An optical ring circuit for modulating light from a light source into an optical signal includes a ring modulator located near a waveguide to couple a light propagating the waveguide, the ring modulator including a pair of electrodes, a signal generator to transmit an electrical signal corresponding to the optical signal, a filter circuit to generate an output signal, wherein the filter circuit includes an adder unit and at least one tap unit having a delay unit and a coefficient unit, wherein the adder unit adds the electrical signal from the signal generator and a signal passed from the tap unit for pre-compensating signal components of the electrical signal by at least twice delay time of the delay unit, and a driver circuit to apply a voltage to the electrodes based on the output signal.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 17, 2020
    Assignees: Mitsubishi Electric Research Laboratories, Inc., Mitsubishi Electric Corporation
    Inventors: Keisuke Kojima, Min Teng, Toshiaki Koike-Akino, Chungwei Lin, Kieran Parsons, Mitsunobu Gotoda, Koichi Akiyama
  • Publication number: 20200327914
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Application
    Filed: June 27, 2020
    Publication date: October 15, 2020
    Applicant: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Publication number: 20200255413
    Abstract: Provided herein are heterocyclic derivative compounds and pharmaceutical compositions comprising said compounds that are useful for inhibiting the growth of gram-negative bacteria. Furthermore, the subject compounds and compositions are useful for the treatment of bacterial infection, such as urinary tract infection and the like.
    Type: Application
    Filed: May 9, 2018
    Publication date: August 13, 2020
    Inventors: Min TENG, Baskar NAMMALWAR, Konstantin TAGANOV, Xiaoming LI, David T. PUERTA
  • Patent number: 10706900
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Publication number: 20200194039
    Abstract: Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Applicant: Intel Corporation
    Inventors: Raymond CHONG, Bee Min TENG, Christopher MOZAK