Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.

Abstract: A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

Abstract: A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.

Abstract: The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.

Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer lining the first trench; and forming a dielectric feature in the first trench.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.

Abstract: Embodiments of the present disclosure provide semiconductor device structures having at least one T-shaped stacked nanosheet transistor to provide increased effective conductive area across the channel regions. In one embodiment, the semiconductor device structure includes a first channel layer formed of a first material, wherein the first channel layer has a first width, and a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer and the second channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.

Abstract: Embodiments of the present disclosure provide semiconductor device structures having at least one T-shaped stacked nanosheet transistor to provide increased effective conductive area across the channel regions. In one embodiment, the semiconductor device structure includes a first channel layer formed of a first material, wherein the first channel layer has a first width, and a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer and the second channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.

Abstract: A semiconductor structure includes a substrate, a pair of first fins extending from the substrate, a pair of second fins extending from the substrate, an isolation feature over the substrate and separating bottom portions of the first and the second fins, a pair of first epitaxial semiconductor features over the pair of first fins respectively, a pair of second epitaxial semiconductor features over the pair of second fins respectively, and a first dielectric feature sandwiched between and separating the pair of first epitaxial semiconductor features. The pair of second epitaxial semiconductor features merge with each other.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.