Patents by Inventor Ming Dou

Ming Dou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160209463
    Abstract: In a test method for eliminating electrostatic charges, at least one test process is firstly performed by a test equipment comprising a tester and a platform, and electrostatic charges are generated on the test equipment in the test process. In the test process, the tester contacts and tests at least one tested integrated circuit (IC) on a test area of the platform, and then the tested IC is removed from the tester and the test area. Next, a conduction device which is grounded is moved to the test area, so that the tester contacts the conduction device to discharge the electrostatic charges to ground. Next, the conduction device is removed from the tester and the test area. Finally, the method returns to the test process to test the next tested IC.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 21, 2016
    Inventors: MING-DOU KER, CHE-HAO CHUANG
  • Patent number: 9343558
    Abstract: A silicon controlled rectifier includes a substrate, a well, a deep doped region, a first doped region, a second doped region, a third doped region, and a fourth doped region. The well is disposed on the substrate and underneath a cell region. The deep doped region is disposed in the well. The first doped region has a first conductivity type, and is disposed in the well. The second doped region and third doped region have the first conductivity type and are disposed on the deep doped region. The fourth doped region has a second conductivity type, and is disposed between the second doped region and the third doped region. The fourth doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region, the second doped region, and the third doped region.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: May 17, 2016
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Ming-Dou Ker, Wen-Tai Wang
  • Patent number: 9224702
    Abstract: A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: December 29, 2015
    Assignee: Amazing Microelectronic Corp.
    Inventors: Ming-Dou Ker, Che-Hao Chuang
  • Patent number: 9190840
    Abstract: An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 17, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Ming-Dou Ker, Chun-Yu Lin, Chang-Tzu Wang
  • Publication number: 20150318692
    Abstract: An active guard ring structure is provided, which is applicable to improving latch-up immunity during the latch-up current test (I-test). The proposed active guard ring structure comprises an I/O circuit and an active protection circuit, wherein the I/O circuit receives a trigger current via an input pad and generates a corresponding bulk current since being triggered. The active protection circuit, connected between the I/O circuit and a core circuit, detects whether the trigger current is a positive or negative current pulse. When an intensity of the trigger current is larger than a threshold value, the active protection circuit controls the I/O circuit to provide a sink or compensation current so as to neutralize the bulk current and to reduce the net current flowing into or sourced from the core circuit, thereby increasing the latch-up resistance and immunity of the core circuit.
    Type: Application
    Filed: August 26, 2014
    Publication date: November 5, 2015
    Inventors: MING-DOU KER, HUI-WEN TSAI
  • Patent number: 9130008
    Abstract: Some embodiments relate to a silicon controlled rectifier (SCR) that includes a current path which couples an SCR anode to an SCR cathode. The current path includes a first vertical current path component coupled to the SCR anode, and a second vertical current path component coupled to the SCR cathode. A horizontal current path component includes a first well region and a second well region that meet at a junction lying along a first plane. The first and second well regions cooperatively span a distance between the first and second vertical current path components. The first and second vertical current path components mirror one another symmetrically about the first plane.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yu Lin, Ming-Dou Ker, Ming Hsien Tsai, Li-Wei Chu, Ming-Hsiang Song
  • Patent number: 9111811
    Abstract: The present invention provides an analog memory cell circuit for the LTPS TFT-LCD. The circuit comprises the first transistor, second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the capacitor. It comprises a plurality of operation period, wherein the transistors are controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal is output in the opposite to the output jack.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 18, 2015
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Li-Wei Chu, Ming-Dou Ker
  • Publication number: 20150171031
    Abstract: A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Applicant: AMAZING MICROELECTRONIC CORP.
    Inventors: Ming-Dou KER, Che-Hao CHUANG
  • Patent number: 9024516
    Abstract: A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block, and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: May 5, 2015
    Assignee: Amazing Microelectronic Corp.
    Inventors: Tung-Yang Chen, Ming-Dou Ker, Ryan Hsin-Chin Jiang
  • Patent number: 9001478
    Abstract: A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: April 7, 2015
    Assignees: National Chiao-Tung University, Himax Technologies Limited
    Inventors: Ming-Dou Ker, Cheng-Cheng Yen, Tung-Yang Chen, Ching-Ling Tsai, Shih-Fan Chen
  • Patent number: 8892202
    Abstract: The disclosure relates to a current stimulator, which comprises a high voltage output module, a voltage control module and a charge pump module. The high voltage output module includes a plurality of stacked transistors, and receives an input control signal able to turn on/off the current stimulator and a first voltage. A second voltage is generated by adding the voltages output by all the transistors to the first voltage and then output to the voltage control module. The voltage control module outputs a voltage control signal able to stabilize the stimulus current for the load according to the second voltage and the load impedance variation. The charge pump regulates the first voltage according to the voltage control signal, and outputs the regulated first voltage to the high voltage output module. Thereby, the current stimulator can adaptively stabilize the stimulus current, responding to load impedance variation.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: November 18, 2014
    Assignee: National Chiao Tung University
    Inventors: Chun-Yu Lin, Yi-Ju Li, Ming-Dou Ker
  • Patent number: 8854778
    Abstract: An electrostatic discharge protection circuit includes an input node coupled to receive an input signal and an output node coupled to output the input signal to an internal circuit. A first inductor is coupled to the input node and to the output node, and a second inductor is coupled to the output node and to a first power supply node through a resistance. A plurality of protection devices are coupled to the first and second inductors and are disposed in parallel with each other.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Wei Chu, Chun-Yu Lin, Shiang-Yu Tsai, Ming-Dou Ker, Ming-Hsien Tsai, Tsun-Lai Hsu, Chew-Pu Jou
  • Patent number: 8842400
    Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: September 23, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Shih-Hung Chen, Kun-Hsien Lin
  • Patent number: 8829775
    Abstract: The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: September 9, 2014
    Assignee: Amazing Microelectric Corp.
    Inventors: Tung-Yang Chen, Ming-Dou Ker, Ryan Hsin-Chin Jiang
  • Patent number: 8773826
    Abstract: A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: July 8, 2014
    Assignee: Amazing Microelectronic Corp.
    Inventors: Federico Agustin Altolaguirre, Ming-Dou Ker, Ryan Hsin-Chin Jiang
  • Patent number: 8749931
    Abstract: An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: June 10, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Fu-Yi Tsai, Chia-Ku Tsai, Yan-Hua Peng, Ming-Dou Ker
  • Patent number: 8743517
    Abstract: ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 3, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Fu-Yi Tsai, Yan-Hua Peng, Chia-Ku Tsai, Ming-Dou Ker
  • Publication number: 20140106064
    Abstract: A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block., and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Applicant: Amazing Microelectronic Corp.
    Inventors: Tung-Yang CHEN, Ming-Dou KER, Ryan Hsin-Chin JIANG
  • Publication number: 20140063663
    Abstract: A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Inventors: Federico Agustin ALTOLAGUIRRE, Ming-Dou Ker, Ryan Hsin-Chin Jiang
  • Patent number: 8649135
    Abstract: A noise filter circuit for an IC is provided. The noise filter circuit comprises a decoupling unit coupled to a power pad of the IC and a current amplifier circuit coupled to the decoupling unit and the power pad of the IC. The decoupling unit generates a first current in response to a transient voltage being on the power pad of the IC. The current amplifier circuit drains a second current from the power pad of the IC according to the first current.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: February 11, 2014
    Assignees: National Chiao-Tung University, Himax Technologies Limited
    Inventors: Ming-Dou Ker, Cheng-Cheng Yen, Tung-Yang Chen