Patents by Inventor Ming Dou

Ming Dou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130314826
    Abstract: An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.
    Type: Application
    Filed: July 31, 2013
    Publication date: November 28, 2013
    Applicants: National Chiao Tung University, UNITED MICROELECTRONICS CORPORATION
    Inventors: Ming-Dou Ker, Chun-Yu Lin, Chang-Tzu Wang
  • Patent number: 8527061
    Abstract: The disclosure relates to a load-adaptive bioelectrical current stimulator, which comprises a current output module, an adaptation module and a control module. The current output module generates a stimulus current to an electrode. The adaptation module detects the electrical status of the stimulus current passing through the electrode and generates a feedback signal to the control module. According to the feedback signal, the control module controls the current output module to stabilize the output status of the stimulus current adaptively. Thereby, the load-adaptive bioelectrical current stimulator can use the feedback control mechanism to regulate the value of the stimulus current to adapt to variation of load impedance.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: September 3, 2013
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Wei-Ling Chen, Chun-Yu Lin
  • Patent number: 8525265
    Abstract: An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 3, 2013
    Assignees: United Microelectronics Corp., National Chiao Tung University
    Inventors: Ming-Dou Ker, Chun-Yu Lin, Chang-Tzu Wang
  • Publication number: 20130221834
    Abstract: The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
    Type: Application
    Filed: May 4, 2012
    Publication date: August 29, 2013
    Inventors: Tung-Yang Chen, Ming-Dou Ker, Ryan Hsin-Chin Jiang
  • Patent number: 8507946
    Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: August 13, 2013
    Assignees: Vanguard International Semiconductor Corporation, National Chiao Tung University
    Inventors: Yeh-Jen Huang, Yeh-Ning Jou, Ming-Dou Ker, Wen-Yi Chen, Chia-Wei Hung, Hwa-Chyi Chiou
  • Patent number: 8498085
    Abstract: An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: July 30, 2013
    Assignee: National Sun Yat-Sen University
    Inventors: Federico A. Altolaguirre, Ming-Dou Ker, Chua-Chin Wang
  • Patent number: 8493700
    Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: July 23, 2013
    Assignee: Elan Microelectronics Corporation
    Inventors: Wu-Tsung Hsihe, Ming-Chun Chou, Ming-Dou Ker
  • Patent number: 8493705
    Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier; an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus; and an ESD clamp circuit that is coupled to the first voltage line.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: July 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, Ming-Hsien Tsai, Ping-Fang Hung, Ming-Hsiang Song
  • Publication number: 20130172958
    Abstract: The disclosure relates to a current stimulator, which comprises a high voltage output module, a voltage control module and a charge pump module. The high voltage output module includes a plurality of stacked transistors, and receives an input control signal able to turn on/off the current stimulator and a first voltage. A second voltage is generated by adding the voltages output by all the transistors to the first voltage and then output to the voltage control module. The voltage control module outputs a voltage control signal able to stabilize the stimulus current for the load according to the second voltage and the load impedance variation. The charge pump regulates the first voltage according to the voltage control signal, and outputs the regulated first voltage to the high voltage output module. Thereby, the current stimulator can adaptively stabilize the stimulus current, responding to load impedance variation.
    Type: Application
    Filed: April 4, 2012
    Publication date: July 4, 2013
    Inventors: Chun-Yu Lin, Yi-ju Li, Ming-Dou Ker
  • Publication number: 20130163127
    Abstract: An electrostatic discharge protection circuit includes an input node coupled to receive an input signal and an output node coupled to output the input signal to an internal circuit. A first inductor is coupled to the input node and to the output node, and a second inductor is coupled to the output node and to a first power supply node through a resistance. A plurality of protection devices are coupled to the first and second inductors and are disposed in parallel with each other.
    Type: Application
    Filed: December 27, 2011
    Publication date: June 27, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Wei CHU, Chun-Yu LIN, Shiang-Yu TSAI, Ming-Dou KER, Ming-Hsien TSAI, Tsun-Lai HSU, Chew-Pu JOU
  • Publication number: 20130155566
    Abstract: A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicants: HIMAX TECHNOLOGIES LIMITED, NATIONAL CHIAO-TUNG UNIVERSITY
    Inventors: MING-DOU KER, Cheng-Cheng Yen, Tung-Yang CHEN, Ching-Ling Tsai, Shih-Fan Chen
  • Patent number: 8422180
    Abstract: An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: April 16, 2013
    Assignee: Faraday Technology Corp.
    Inventors: Chun-Yu Lin, Ming-Dou Ker, Fu-Yi Tsai
  • Patent number: 8421506
    Abstract: An output buffer with process and temperature compensation comprises an enable terminal, a clock generator, a PMOS threshold voltage detector, an NMOS threshold voltage detector, a first comparator, a second comparator, a first compensation code generator, a second compensation code generator and an output buffer stage, wherein the output buffer stage has an output stage, the output buffer stage means for controlling a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: April 16, 2013
    Assignee: National Sun Yat-Sen University
    Inventors: Chua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu, Ming-Dou Ker
  • Publication number: 20130088801
    Abstract: An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line.
    Type: Application
    Filed: April 25, 2012
    Publication date: April 11, 2013
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Fu-Yi Tsai, Chia-Ku Tsai, Yan-Hua Peng, Ming-Dou Ker
  • Publication number: 20130057992
    Abstract: An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.
    Type: Application
    Filed: August 20, 2012
    Publication date: March 7, 2013
    Applicant: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Federico A. Altolaguirre, Ming-Dou Ker, Chua-Chin Wang
  • Publication number: 20130044397
    Abstract: ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate.
    Type: Application
    Filed: June 21, 2012
    Publication date: February 21, 2013
    Applicant: FARADAY TECHNOLOGY CORPORATION
    Inventors: Fu-Yi Tsai, Yan-Hua Peng, Chia-Ku Tsai, Ming-Dou Ker
  • Patent number: 8378737
    Abstract: A charge pump circuit includes at least one stage between an input end and an output end. The at least one stage includes a first CMOS transistor coupled with a first capacitor and a second CMOS transistor coupled with a second capacitor. The at least one stage is capable of receiving a first timing signal and a second timing signal for pumping an input voltage at the input end to an output voltage at the output end. During a transitional period of the first timing signal and the second timing signal, the at least one stage is capable of substantially turning off at least one of the first CMOS transistor and the second CMOS transistor for substantially reducing leakage currents flowing through at least one of the first CMOS transistor and the second CMOS transistor.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Dou Ker, Yi-Hsin Weng
  • Patent number: 8379354
    Abstract: Self-triggered Multi-finger SCRs used in ESD protection circuitry capable of turning on all SCR fingers of the multi-finger SCRs include a first source, a second source, N SCR units, (N?1) diodes, and N resistors. Each of the N SCR units includes a first node, a second node coupled to the second source, and a trigger node. An nth diode of the (N?1) diodes is coupled between a first node of an nth SCR unit and a trigger node of an (n+1)th SCR unit. An nth resistor is coupled between the first node of the nth SCR unit and the first source, wherein n and N are integers. The (N?1) diodes can be replaced by directly coupled the first node of the nth SCR unit to the trigger node of the (n+1)th SCR unit when a trigger pulse is applied at the trigger node of a first SCR unit.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: February 19, 2013
    Assignees: United Microelectronics Corp., National Chiao-Tung University
    Inventors: Ming-Dou Ker, Chun-Yu Lin, Chang-Tzu Wang
  • Patent number: 8367457
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: February 5, 2013
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • Patent number: 8339757
    Abstract: An ESD protection circuit with multiple domains, which comprises: an ESD protection device, coupled between a first power supplying line and a first ground line; a first internal circuit, having a first terminal coupled to the first power supplying line; a first switch, coupled between a second terminal of the first internal circuit and a second ground line; and a first ESD detection circuit, coupled to the first switch, for detecting an ESD signal, and controls the first switch to be non-conductive when the ESD signal occurs.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: December 25, 2012
    Assignee: Faraday Technology Corp.
    Inventors: Fu-Yi Tsai, Ming-Dou Ker