Patents by Inventor Ming-Fang Wang

Ming-Fang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916131
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Publication number: 20230331036
    Abstract: A car wheel rim decoration cover fastening structure includes a wheel rim, a locking ring, a wheel rim cover, and a central cap. The wheel rim has a rim body and a central hole. The wheel rim has an inner flange formed in the central hole. The locking ring is mounted in the central hole of the wheel rim and locked on the inner flange of the wheel rim. The wheel rim cover has multiple locking blocks secured to the rim body of the wheel rim. The wheel rim cover corresponds to the locking ring. The central cap extends through the center of the wheel rim cover and is locked on the inside of the locking ring. The central cap presses the wheel rim cover. Thus, the wheel rim cover is fixed and will not be detached.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 19, 2023
    Inventor: Ming-Fang Wang
  • Publication number: 20190030948
    Abstract: An auxiliary fastening device includes a plurality of auxiliary male fasteners and a plurality of auxiliary female fasteners connected with the auxiliary male fasteners. Each of the auxiliary male fasteners includes a male body having a first side provided with a securing face secured on the wheel disk and a second side provided with a locking piece. Each of the auxiliary female fasteners includes a female body having a first side provided with a securing face secured on the ornamental cover and a second side provided with a locking groove locked onto the locking piece of each of the auxiliary male fasteners to secure the ornamental cover to the wheel disk. Thus, the auxiliary fastening device provides an auxiliary locking function so that the ornamental cover is locked onto the wheel disk solidly and stably.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventor: Ming-Fang Wang
  • Patent number: 10005316
    Abstract: A wheel disk structure includes a wheel cover and a fastening unit. The wheel cover has a side provided with a plurality of projecting members each having a periphery provided with at least two connecting seats. The fastening unit includes a plurality of locking members detachably mounted on the connecting seats of the projecting members, and a plurality of elastic members mounted between the projecting members and the locking members. Each of the locking members has a first side provided with a locking recess corresponding to each of the projecting members and mounted on each of the elastic members. Each of the locking members has a second side provided with a protrusion. Thus, the fastening unit is detachable and can be removed and replaced when being worn out, so that the wheel cover can be reused.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 26, 2018
    Assignee: Superior Crown Material Co., Ltd.
    Inventor: Ming-Fang Wang
  • Publication number: 20180099524
    Abstract: A wheel disk structure includes a wheel cover and a fastening unit. The wheel cover has a side provided with a plurality of projecting members each having a periphery provided with at least two connecting seats. The fastening unit includes a plurality of locking members detachably mounted on the connecting seats of the projecting members, and a plurality of elastic members mounted between the projecting members and the locking members. Each of the locking members has a first side provided with a locking recess corresponding to each of the projecting members and mounted on each of the elastic members. Each of the locking members has a second side provided with a protrusion. Thus, the fastening unit is detachable and can be removed and replaced when being worn out, so that the wheel cover can be reused.
    Type: Application
    Filed: October 12, 2016
    Publication date: April 12, 2018
    Inventor: Ming-Fang Wang
  • Patent number: 8785272
    Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang
  • Publication number: 20130234498
    Abstract: A wheel cover and a method for making and packaging it are disclosed. The wheel cover includes a main body (1), and a plurality of locking members (13). Each of the locking members is formed integrally on the inner face of the main body. Each of the locking members has a first end provided with a support portion (134) connected with the main body and a second end provided with a retaining portion (133). Thus, the support portion of each of the locking members is bendable relative to the main body so as to reduce a whole height of each of the locking members relative to the main body.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 12, 2013
    Inventor: Ming-Fang Wang
  • Publication number: 20110318915
    Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
    Type: Application
    Filed: September 1, 2011
    Publication date: December 29, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang
  • Patent number: 8012824
    Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: September 6, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang
  • Patent number: 7393766
    Abstract: A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: July 1, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fang Wang, Chien-Hao Chen, Liang-Gi Yao, Shih-Chang Chen
  • Publication number: 20080083248
    Abstract: The present invention discloses a bead ornament structure that includes: two half bead bodies, each having a level attaching surface and a protruding external surface protruded from the attaching surface; and a partition base having a level surface disposed on two lateral bases of the partition base, each having a circular flange extended around a section of the partition base, such that the two half bead bodies are embedded into the circular flange with an appropriate tightness by the level attaching surface and attached onto the base, and the periphery of the two half bead bodies is bound and fixed by the circular flange extended from the partition base.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 10, 2008
    Inventors: Ming-Fang Wang, Hsueh-Hu Chiang
  • Patent number: 7351994
    Abstract: At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. A method of forming the at least one high-k device.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: April 1, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Liang-Gi Yao, Tien-Chih Chang, Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang
  • Patent number: 7314255
    Abstract: The invention structure of wheel rim cover includes: a cover body whose disc surface has a plurality of spokes separated by openings; many fasteners are set on an outer edge of a rearward end hole of each opening. The fasteners are grouped surrounding the end hole of a same opening, and are jointly supported by a spring ring. The whole cover body can make use of the fasteners to latch on the end hole of the opening of a targeted wheel rim to fasten the cover body on the wheel rim.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: January 1, 2008
    Assignee: Kuan Hsings Enterprise Corp.
    Inventor: Ming-Fang Wang
  • Patent number: 7303996
    Abstract: A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: December 4, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fang Wang, Tuo-Hung Hou, Kai-Lin Mai, Liang-Gi Yao, Shih-Chang Chen
  • Patent number: 7271450
    Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: September 18, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tuo-Hung Ho, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Chih-Chang Chen
  • Publication number: 20070096545
    Abstract: A wheel rim covering structure of the invention includes: one cover body, which has a cover surface and ring spoke edge is formed on it. Many costal bodies and engraved holes are sit on the cover surface, and the shrinking hole edge of each engraved hole would form an end hole at the backside of the cover surface. The hole edge is equipped with a plastic made fastener assembly which was formed as one with the cover body. Such fastener assembly each has a suitable length stem. A buckling part would be set at one end of the stem to co-surround to establish the first ring diameter and has the first height, from ring spoke edge to the end of the fastener assembly part. By means of stem of the fastener assembly extends into the engraved holes of wheel rim and the buckling part would buckle up the inner edge of each engraved hole respectively. Hence, the whole wheel rim cover body could be poisoned stably.
    Type: Application
    Filed: November 15, 2005
    Publication date: May 3, 2007
    Applicant: Kuan Hsings Enterprise Corp.
    Inventor: Ming-Fang Wang
  • Publication number: 20060246698
    Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
    Type: Application
    Filed: June 16, 2006
    Publication date: November 2, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company. Ltd.
    Inventors: Liang-Gi Yao, Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang
  • Patent number: 7087480
    Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: August 8, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, Ming-Fang Wang, Shih-Chang Chen, Mon-Song Liang
  • Patent number: 7071066
    Abstract: A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: July 4, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fang Wang, Chia-Lin Chen, Chih-Wei Yang, Chi-Chun Chen, Tuo-Hung Hou, Yeou-Ming Lin, Liang-Gi Yao, Shih-Chang Chen
  • Patent number: RE43673
    Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: September 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Shih-Chang Chen