Patents by Inventor Ming-Heng Tsai

Ming-Heng Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240243192
    Abstract: A semiconductor device structure includes a dielectric wall disposed over a substrate, a plurality of first semiconductor layers vertically stacked and extended outwardly from a first side of the dielectric wall, a plurality of second semiconductor layers vertically stacked and extended outwardly from a second side of the dielectric wall, a first epitaxial source/drain (S/D) feature disposed on the first side of the dielectric wall, a second epitaxial S/D feature disposed on the second side of the dielectric wall, a first bottom dielectric layer extended outwardly from the first side of the dielectric wall, and a second bottom dielectric layer extended outwardly from the second side of the dielectric wall.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Ta-Chun LIN, JHON JHY LIAW
  • Patent number: 12040237
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
  • Publication number: 20240224486
    Abstract: A device includes a first transistor, a second transistor, and a dielectric wall. The first transistor includes first semiconductor channel layers, a first gate structure, and first source/drain structures on opposite sides of the first gate structure. The second transistor includes second semiconductor channel layers, a second gate structure, and second source/drain structures on opposite sides of the second gate structure. The dielectric wall includes a first sidewall abutting side surfaces of the first semiconductor channel layers in a first cross-sectional view taken along a longitudinal axis of the first gate structure, the first sidewall of the dielectric wall also abutting side surfaces of second semiconductor channel layers in a second cross-sectional view taken along a longitudinal axis of the second gate structure, in which in a top view, the first sidewall of the dielectric wall has a stepped profile.
    Type: Application
    Filed: January 3, 2023
    Publication date: July 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Ta-Chun LIN, Jhon Jhy LIAW
  • Publication number: 20240162336
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure extends above the isolation structure, and the first stack structure includes a plurality of first nanostructures along a first direction. The semiconductor structure also includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of second nanostructures along the first direction. A first dielectric wall between the first stack structure and the second stack structure, and the first dielectric wall is directly over a first portion of the isolation structure and surrounded by a second portion of the isolation structure, and a top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.
    Type: Application
    Filed: March 8, 2023
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG
  • Publication number: 20240145555
    Abstract: Semiconductor structures and processes are provided. A semiconductor structure of the present disclosure includes a first base portion and a second base portion extending lengthwise along a first direction, a first source/drain feature disposed over the first base portion, a second source/drain feature disposed over the second base portion, a center dielectric fin sandwiched between the first source/drain feature and the second source/drain feature along a second direction perpendicular to the first direction, and a source/drain contact disposed over the first source/drain feature, the second source/drain feature and the center dielectric fin. A portion of the source/drain contact extends between the first source/drain feature and the second source/drain feature along the second direction.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Heng Tsai, Chih-Hao Chang, Chun-Sheng Liang, Ta-Chun Lin
  • Publication number: 20240113121
    Abstract: Semiconductor devices are provided. A semiconductor device includes a first well region having a first conductivity type, a second well region having a second conductivity type, a cell, and a pickup tap cell. The cell includes a first forksheet structure. The first forksheet structure includes a first transistor formed over the first well region, a second transistor formed over the second well region, and a first wall structure disposed on and extending along an interface between the first and second well regions. The first transistor and the second transistor are disposed on opposite sides of the first wall structure. The pickup tap cell includes a nanosheet structure. The nanosheet structure includes a pickup transistor formed over the second well region. Source/drain features of the first transistor and the pickup transistor have the second conductivity type, and source/drain features of the second transistor have the first conductivity type.
    Type: Application
    Filed: February 16, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Heng TSAI, Ta-Chun LIN
  • Publication number: 20240088149
    Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 15, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Ming-Heng TSAI, Huang-Chao CHANG, Chun-Sheng LIANG, Chih-Hao CHANG, Jhon Jhy LIAW
  • Patent number: 11923455
    Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Sheng Liang, Kuo-Hua Pan, Hsin-Che Chiang, Ming-Heng Tsai
  • Patent number: 11450667
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a well, an oxidation layer, a gate electrode and a shared source/drain electrode. The substrate has a first surface and a second surface opposite to each other. The well is formed in the substrate. The substrate and the well have a first conductivity type and a second conductivity type respectively. The oxidation layer is formed in the well. The gate electrode is formed above the first surface and has a first opening. The shared source/drain electrode is formed near the first surface in the oxidation layer and exposed from the first opening. The shared source/drain electrode has the first conductivity type.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: September 20, 2022
    Assignee: Raydium Semiconductor Corporation
    Inventors: Kuan-Hung Chou, Po-Chang Jen, Ming-Heng Tsai
  • Publication number: 20220285224
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Pei-Lin WU, Yi-Ren CHEN, Shih-Hsun CHANG
  • Patent number: 11348841
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate, wherein the gate stack has a first portion and a second portion under the first portion, and the first portion is wider than the second portion. The semiconductor device structure includes a first spacer and a second spacer over opposite sides of the gate stack. The first spacer has a first upper portion and a first lower portion, the second spacer has a second upper portion and a second lower portion. The first spacer has a first recess, the first upper portion is between the first recess and the gate stack, the first lower portion is under the first recess, and the first recess has a first inner wall facing away from the gate stack.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
  • Publication number: 20210305421
    Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Sheng Liang, Kuo-Hua Pan, Hsin-Che Chiang, Ming-Heng Tsai
  • Patent number: 11038059
    Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Sheng Liang, Kuo-Hua Pan, Hsin-Che Chiang, Ming-Heng Tsai
  • Patent number: 10971606
    Abstract: A method for manufacturing a semiconductor device includes forming a shallow trench isolation (STI) structure surrounding a pair of semiconductor fins; forming a dummy gate layer over the STI structure and the semiconductor fins; etching a first portion of the dummy gate layer to form a trench through the dummy gate layer until the STI structure is exposed, in which the trench extends between the semiconductor fins along a lengthwise direction of the semiconductor fins; forming an insulating structure in the trench through the dummy gate layer; after forming the insulating structure extending through the dummy gate layer, patterning the dummy gate layer to form a pair of dummy gate structures each of which is across a respective one of the semiconductor fins; and replacing the dummy gate structures with a pair of metal gate structures.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 10964815
    Abstract: A semiconductor device includes a substrate, a gate disposed over the substrate, a source/drain disposed in the substrate at two sides of the gate, and an insulating layer disposed over sidewalls of the gate and at least a portion of a surface of the source/drain. In some embodiments, the insulating layer includes a first side facing the gate or the source, and includes a second side opposite to the first side. The insulating layer includes dopants, and a concentration of the dopants is reduced from the second side to the first side of the insulating layer.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hong-Nien Lin, Ming-Heng Tsai, Yong-Yan Lu, Chun-Sheng Liang, Jeng-Ya Yeh
  • Publication number: 20200395253
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate, wherein the gate stack has a first portion and a second portion under the first portion, and the first portion is wider than the second portion. The semiconductor device structure includes a first spacer and a second spacer over opposite sides of the gate stack. The first spacer has a first upper portion and a first lower portion, the second spacer has a second upper portion and a second lower portion. The first spacer has a first recess, the first upper portion is between the first recess and the gate stack, the first lower portion is under the first recess, and the first recess has a first inner wall facing away from the gate stack.
    Type: Application
    Filed: August 28, 2020
    Publication date: December 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Pei-Lin WU, Yi-Ren CHEN, Shih-Hsun CHANG
  • Patent number: 10763178
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
  • Publication number: 20200091153
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a well, an oxidation layer, a gate electrode and a shared source/drain electrode. The substrate has a first surface and a second surface opposite to each other. The well is formed in the substrate. The substrate and the well have a first conductivity type and a second conductivity type respectively. The oxidation layer is formed in the well. The gate electrode is formed above the first surface and has a first opening. The shared source/drain electrode is formed near the first surface in the oxidation layer and exposed from the first opening. The shared source/drain electrode has the first conductivity type.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 19, 2020
    Inventors: KUAN-HUNG CHOU, PO-CHANG JEN, MING-HENG TSAI
  • Publication number: 20200043433
    Abstract: A source driver with data dependent shared buffer design including a first data judging unit, a first buffer, a second buffer and a first output switch unit is disclosed. The first data judging unit judges whether a first input data and a second input data having a first polarization are the same. The first buffer and second buffer, coupled to the first data judging unit, are used to temporarily store the first input data and second input data respectively. The output switch unit is coupled to the first data judging unit, an output terminal of first buffer and an output terminal of second buffer respectively. When a judging result of first data judging unit is YES, the first data judging unit turns off the first buffer or second buffer and conducts the first output switch unit, so that the output terminals of first buffer and second buffer are coupled.
    Type: Application
    Filed: July 24, 2019
    Publication date: February 6, 2020
    Inventors: MING-HENG TSAI, CHIH-HSIEH JEN, CHIH-CHUAN HUANG
  • Publication number: 20200044074
    Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.
    Type: Application
    Filed: July 17, 2019
    Publication date: February 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Sheng Liang, Kuo-Hua Pan, Hsin-Che Chiang, Ming-Heng Tsai