Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

Abstract: A display panel including a bottom plate, a plurality of display modules, and a plurality of connection pixel packages is provided. The display modules are tiled in an array arrangement on the bottom plate. Each of the display modules includes a circuit substrate and a plurality of display pixels. The circuit substrate includes a plurality of connection electrodes. The display pixels are disposed on the circuit substrate and at least one of the display pixels has at least one second pixel unit. Each of the connection pixel packages includes at least one first pixel unit. The connection pixel packages are disposed on the connection electrodes of the adjacent circuit substrates to connect the display modules. A light emitting surface of the at least one first pixel unit and a light emitting surface of the at least one second pixel unit are coplanar.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.

Abstract: Devices, systems, and processes are disclosed herein for separating a substance from a sample using size-exclusion chromatography (SEC) in a compact and configurable apparatus (referred to as a divider or separator). The divider separates the substance using SEC by having the sample flow through a conduit that has a length greater than the distance between an inlet and an outlet of the divider.

Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

Abstract: A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.

Abstract: An IC includes power and reference nodes, a protection circuit, and a gate driver. The protection circuit includes a series of diode-configured enhancement-mode n-type HEMTs coupled between the power and reference nodes and including a voltage tap, a first enhancement-mode n-type HEMT including a gate coupled to the voltage tap and a source terminal coupled to the reference node, and a second enhancement-mode n-type HEMT including a gate coupled to a drain terminal of the first n-type HEMT and a source terminal coupled to the reference node. The gate driver includes a third enhancement-mode n-type HEMT including a gate coupled to a drain terminal of the second n-type HEMT, a fourth enhancement-mode n-type HEMT including a gate coupled to a source terminal of the third n-type HEMT and a source terminal coupled to the reference node, and an output terminal coupled to a drain terminal of the fourth n-type HEMT.

Abstract: A circuit includes power supply and reference nodes, a protection circuit including a first output terminal and first and second series of n-type HEMTs coupled between the power supply and reference nodes, and a gate driver including a second output terminal and third through fifth series of n-type HEMTs coupled between the power supply and reference nodes. The first HEMT series controls a first node voltage responsive to a power supply node voltage, the second HEMT series controls a first output terminal voltage responsive to the first node voltage, the third HEMT series controls an internal signal on a second node responsive to the first output terminal voltage and to an input signal, the fourth HEMT series controls a third node voltage responsive to the internal signal, and the fifth HEMT series controls a signal at the second output terminal responsive to the internal signal and the third node voltage.

Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.

Abstract: A circuit includes power supply and reference nodes, a protection circuit including a first output terminal and first and second series of n-type HEMTs coupled between the power supply and reference nodes, and a gate driver including a second output terminal and third through fifth series of n-type HEMTs coupled between the power supply and reference nodes. The first HEMT series controls a first node voltage responsive to a power supply node voltage, the second HEMT series controls a first output terminal voltage responsive to the first node voltage, the third HEMT series controls an internal signal on a second node responsive to the first output terminal voltage and to an input signal, the fourth HEMT series controls a third node voltage responsive to the internal signal, and the fifth HEMT series controls a signal at the second output terminal responsive to the internal signal and the third node voltage.

Abstract: A circuit includes a power supply voltage node having a power supply voltage level, a protection circuit that generates a first signal having first and second logical voltage levels based on the power supply voltage level, and a gate driver. The gate driver includes a first n-type HEMT between the power supply voltage node and a first node, a second n-type HEMT between the first node and a power supply reference node, and a DCFL circuit between the first node and an output terminal. A gate of the first n-type HEMT receives the first signal, a gate of the second n-type HEMT receives a second signal, and the DCFL circuit generates a third signal at the output terminal based on the second signal when the first signal has the first logical voltage level, and as a DC voltage level when the first signal has the second logical voltage level.

Abstract: A filter structure includes a ground plane in a first metal layer of an integrated circuit (IC) package, a plate in a second metal layer of the IC package, a dielectric layer between the ground plane and the plate, the ground plane, the dielectric layer, and the plate thereby being configured as a capacitive device, and an inductive device in a third metal layer of the IC package. The inductive device is electrically connected to the plate, and the plate and the inductive device are configured to have a resonance frequency greater than 1 GHz.

Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.