Abstract: A computing device, an operation method of the computing device, and a system on chip are provided. The computing device includes an operator and a resource allocation manager. The operator includes multiple arithmetic units. The resource allocation manager is coupled to the operator and allocates the arithmetic units to a deep learning accelerator and a vector processor for use according to an amount of calculation of the deep learning accelerator and an amount of calculation of the vector processor. The operator receives a first operation request and a second operation request from the deep learning accelerator and the vector processor respectively, uses a first arithmetic unit group of the arithmetic units to perform a calculation of the first operation request, and uses a second arithmetic unit group of the arithmetic units to perform a calculation of the second operation request according to an allocation result.

Abstract: An authentication system and an authentication method are provided. The electronic device of the authentication system includes a controller, a processor and a key module, wherein the processor performs an application program. In a binding phase, the application device generates a digest file according to key factor information and a selection strategy, and stores the digest file in a digest table of the electronic device. In a checking phase, the application program determines whether the controller corresponds to a binding device according to the digest file and the key factor information. If the controller corresponded to the binding device, in an authentication phase, the controller performs an authentication operation of a U2F service with a server device according to the digest file corresponding to the binding device in response to a pressing of the key module.

Abstract: A charging service method includes transmitting information of a communication device to a charging station, transmitting information of the charging station to the communication device, acquiring available service information of the charging station from a charging station server according to the information of the charging station, selecting at least one service option for generating charging service information, transmitting the charging service information to the charging station server, generating charging station certification information to the communication device, relaying the charging station certification information from the communication device to the charging station, and enabling a charging function of the charging station to charge the communication device after the charging station certification information is received by the charging station.

Abstract: A timing controller, a display apparatus, and an operation method thereof are provided. The display apparatus includes a display panel and a timing controller. The timing controller includes a refresh mark controller and a pixel controller. The refresh mark controller includes a refresh mark table, and a plurality of refresh marks in the refresh mark table correspond to a plurality of sub-regions of a display region in the display panel. The refresh mark controller determines whether the sub-regions need to be refreshed according to an image signal and responds to a specific sub-region required to be refreshed to adjust a specific refresh mark according to a mapping ratio. The pixel controller sequentially looks up whether the refresh marks in the refresh mark table are adjusted, obtains the sub-regions corresponding to the adjusted refresh marks according to the mapping ratio, and performs a pixel refresh operation to the sub-regions.

Abstract: The disclosure provides a bistable display device and a driving circuit. The bistable display device includes a display panel and the above-described driving circuit, wherein the driving circuit includes a source driver, a first image buffer, a second image buffer, and a timing controller. The source driver is coupled to the display panel to drive the display panel according to a pixel signal. The timing controller is coupled to the first image buffer, the second image buffer, and the source driver. The timing controller alternately selects a first image signal temporarily stored in the first image buffer and a second image signal temporarily stored in the second image buffer as a current image signal and a previous image signal. The timing controller performs a look-up mechanism based on the current image signal and the previous image signal to generate the pixel signal.

Abstract: The disclosure provides a bistable display device and a driving circuit. The bistable display device includes a display panel and the above-described driving circuit, wherein the driving circuit includes a source driver, a first image buffer, a second image buffer, and a timing controller. The source driver is coupled to the display panel to drive the display panel according to a pixel signal. The timing controller is coupled to the first image buffer, the second image buffer, and the source driver. The timing controller alternately selects a first image signal temporarily stored in the first image buffer and a second image signal temporarily stored in the second image buffer as a current image signal and a previous image signal. The timing controller performs a look-up mechanism based on the current image signal and the previous image signal to generate the pixel signal.

Abstract: An authentication system and an authentication method are provided. The electronic device of the authentication system includes a controller, a processor and a key module, wherein the processor performs an application program. In a binding phase, the application device generates a digest file according to key factor information and a selection strategy, and stores the digest file in a digest table of the electronic device. In a checking phase, the application program determines whether the controller corresponds to a binding device according to the digest file and the key factor information. If the controller corresponded to the binding device, in an authentication phase, the controller performs an authentication operation of a U2F service with a server device according to the digest file corresponding to the binding device in response to a pressing of the key module.

Abstract: A timing controller, a display apparatus, and an operation method thereof are provided. The display apparatus includes a display panel and a timing controller. The timing controller includes a refresh mark controller and a pixel controller. The refresh mark controller includes a refresh mark table, and a plurality of refresh marks in the refresh mark table correspond to a plurality of sub-regions of a display region in the display panel. The refresh mark controller determines whether the sub-regions need to be refreshed according to an image signal and responds to a specific sub-region required to be refreshed to adjust a specific refresh mark according to a mapping ratio. The pixel controller sequentially looks up whether the refresh marks in the refresh mark table are adjusted, obtains the sub-regions corresponding to the adjusted refresh marks according to the mapping ratio, and performs a pixel refresh operation to the sub-regions.

Abstract: A charging service method includes transmitting information of a communication device to a charging station, transmitting information of the charging station to the communication device, acquiring available service information of the charging station from a charging station server according to the information of the charging station, selecting at least one service option for generating charging service information, transmitting the charging service information to the charging station server, generating charging station certification information to the communication device, relaying the charging station certification information from the communication device to the charging station, and enabling a charging function of the charging station to charge the communication device after the charging station certification information is received by the charging station.

Abstract: A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved.

Abstract: The present invention provides a control device of the memory, which accelerates the memory to execute iterant commands. This control device includes a micro-controller unit, a controller, a block information table and a state machine. Among them, the micro-controller unit is used to issue a command to operate the memory, which contains several blocks. The controller is coupled between the memory and the micro-controller unit. When it determines the command needs not be executed repeatedly, the micro-controller unit would issue the command through the control device. When the command is determined necessary for repetitive execution, the state machine would repeatedly carry out this command. The state machine performs an analysis based on the state of every block in the block information table and executes repetitively the command accordingly. It also updates the state information on the blocks in the table accordingly.

Abstract: A class-D amplifier and a method of generating a multi-level output signal thereof are provided. The class-D amplifier includes a controlling logic circuit and an output module. The controlling logic circuit analyzes the amplitude of an input signal to generate a voltage modifying signal. A power supply provides a voltage according to the voltage modifying signal. The controlling logic circuit generates controlling signals according to the input signal. The output module generates an output signal to drive a load according to the voltage and the controlling signals. In other words, the resolution of the amplitude of the output signal is increased by modifying the voltage, and a signal to noise ratio is then increased.

Abstract: An integrated storage device and a control method thereof are provided. The integrated storage device includes an interface controller, a microcontroller, a plurality of non-volatile storage devices, and a channel link controller. The interface controller retrieves a master control signal and a slave control signal sent by a motherboard. The microcontroller generates a selecting signal. The non-volatile storage devices have at least two storage types. The non-volatile storage devices are divided into a first group of storage device and a second group of storage device according to the selecting signal. The channel link controller respectively controls the first group of storage device and the second group of storage device according to the master control signal and the slave control signal. Thereby, the accessing efficiency of the integrated storage device is increased.

Abstract: An auto-addressing method for a series circuit and an auto-detecting method for detecting the number of circuits connected in series are disclosed. The series circuit includes a number of same integrated circuits connected in series. The auto-detecting method is based on the auto-addressing method. In the auto-addressing method, the integrated circuits are enabled to transmit an initial address command sequentially. Each integrated circuit is provided with corresponding address information upon receiving the initial address command.

Abstract: A test board for wafer level semiconductor testing is disclosed. The test board comprises a plurality of wires and microelectronic devices; and a plurality of test sockets on an upper surface of the test board. Each test socket comprises: a base member configured for attachment to the test board with a first set of screws, wherein the base member has a central opening exposing a portion of the underlying test board; an anisotropic conductive film disposed within the central opening of the base member; a chip to be tested, disposed on the anisotropic conductive film within the central opening of the base member; and a cover member overlying the chip, attached to the base member with a second set of screws.

Abstract: A class-D amplifier and a method of generating a multi-level output signal thereof are provided. The class-D amplifier includes a controlling logic circuit and an output module. The controlling logic circuit analyzes the amplitude of an input signal to generate a voltage modifying signal. A power supply provides a voltage according to the voltage modifying signal. The controlling logic circuit generates controlling signals according to the input signal. The output module generates an output signal to drive a load according to the voltage and the controlling signals. In other words, the resolution of the amplitude of the output signal is increased by modifying the voltage, and a signal to noise ratio is then increased.

Abstract: A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved.

Abstract: A control device for a memory is provided. The control device includes a micro-control unit (MCU), a command queue, a command sequencer, and a table. The control device is coupled to the memory and is used for controlling the memory to execute an operation. In which, the MCU outputs a control signal according to the operation. The command sequencer sequentially stores command sets required by the execution of the operation according to the control signal, and each command set includes plural commands. The command queue sequentially stores command set contents according to the order of the corresponding command sets. The table stores a target address of the memory required by the execution of the operation.

Abstract: A test board for wafer level semiconductor testing is disclosed. The test board comprises a plurality of wires and microelectronic devices; and a plurality of test sockets on an upper surface of the test board. Each test socket comprises: a base member configured for attachment to the test board with a first set of screws, wherein the base member has a central opening exposing a portion of the underlying test board; an anisotropic conductive film disposed within the central opening of the base member; a chip to be tested, disposed on the anisotropic conductive film within the central opening of the base member; and a cover member overlying the chip, attached to the base member with a second set of screws.

Abstract: The present invention provides a control device of the memory, which accelerates the memory to execute iterant commands. This control device includes a micro-controller unit, a controller, a block information table and a state machine. Among them, the micro-controller unit is used to issue a command to operate the memory, which contains several blocks. The controller is coupled between the memory and the micro-controller unit. When it determines the command needs not be executed repeatedly, the micro-controller unit would issue the command through the control device. When the command is determined necessary for repetitive execution, the state machine would repeatedly carry out this command. The state machine performs an analysis based on the state of every block in the block information table and executes repetitively the command accordingly. It also updates the state information on the blocks in the table accordingly.