Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

Abstract: A method and apparatus of detecting the states of a battery involve passing test-oriented charging and discharging pulse pair to a battery under test, and retrieving parameters of the battery, such as voltage, current, and temperature, which respond to the charging and discharging pulse pair, so as to estimate the battery states. The battery states include information pertaining to open-circuit voltage, internal resistance, capacitance, state of charge, and state of health of the battery. The battery state-related information is conducive to quick battery state detection and grading.

Abstract: A thin-film fingerprint sensor package primarily comprises a fingerprint sensor chip, a plurality of bumps, a wiring film with a plurality of leads and at least an encapsulant to encapsulate the bumps. A sensing area is formed on an active surface of the fingerprint sensor chip. The bumps are disposed on the active surface and located at two opposing sides of the sensing area. The wiring film has an opening to expose the sensing area. Each lead has an inner end and an outer end. The inner ends are located at two opposing sides of the opening and are bonded to the bumps. Preferably, the wiring film has a flexible extension and the outer ends of the leads are rerouted to the extension for external electrical connections.

Abstract: A thin-film fingerprint sensor package primarily comprises a fingerprint sensor chip, a plurality of bumps, a wiring film, an encapsulant and a metal base to mechanically hold the fingerprint sensor chip. A sensing area is formed on the active surface of the fingerprint sensor chip. The bumps are disposed on the active surface. The wiring film has an opening to expose the sensing area and comprises a plurality of leads bonded to the bumps. The wiring film further has a ground lead electrically connecting the fingerprint sensor chip to the metal base. Therefore, the fingerprint sensor package can provide ESD protection during fingerprint recognition to avoid the damage of the fingerprint sensor chip.

Abstract: A thin-film fingerprint sensor package primarily comprises a fingerprint sensor chip, a plurality of bumps, a wiring film, an encapsulant and a metal base to mechanically hold the fingerprint sensor chip. A sensing area is formed on the active surface of the fingerprint sensor chip. The bumps are disposed on the active surface. The wiring film has an opening to expose the sensing area and comprises a plurality of leads bonded to the bumps. The wiring film further has a ground lead electrically connecting the fingerprint sensor chip to the metal base. Therefore, the fingerprint sensor package can provide ESD protection during fingerprint recognition to avoid the damage of the fingerprint sensor chip.

Abstract: A thin-film fingerprint sensor package primarily comprises a fingerprint sensor chip, a plurality of bumps, a wiring film with a plurality of leads and at least an encapsulant to encapsulate the bumps. A sensing area is formed on an active surface of the fingerprint sensor chip. The bumps are disposed on the active surface and located at two opposing sides of the sensing area. The wiring film has an opening to expose the sensing area. Each lead has an inner end and an outer end. The inner ends are located at two opposing sides of the opening and are bonded to the bumps. Preferably, the wiring film has a flexible extension and the outer ends of the leads are rerouted to the extension for external electrical connections.

Abstract: A chip package including a flexible substrate, a plurality of conductive plugs, a wiring layer, and a chip is provided. The flexible substrate has a first surface and a second surface opposite to the first surface. The conductive plugs pass through the flexible substrate. The wiring layer is located on the first surface and has a plurality of inner leads electrically connected to the conductive plugs respectively. The chip has an active surface and a plurality of bumps on the active surface, wherein the chip is disposed on the second surface of the flexible substrate and connected with the conductive plugs by the bumps. As bumps on the chip are electrically connected to the conductive plugs by hot pressing, the chip is quickly and reliably electrically connected to the inner leads.

Abstract: A packaging process for improving effective chip-bonding area is disclosed in the present invention. An A-stage liquid paste is formed on a substrate and partially cured to become a B-stage film layer. The B-stage film layer is maintained without fully cured passing through a chip-attaching step and an electrically connecting step. During the molding step, the packing pressure for the molding compound (1000 psi˜1500 psi) is larger than the chip attaching pressure for enabling the B-stage film layer to be closely compressed in order to improve effective chip-bonding area. The B-stage film layer and the molding compound are cured simultaneous in the molding step.

Abstract: This invention relates to a dental floss assembly, which comprises a holder also for receiving the dental floss, a locating member mounted at the front portion of the holder, a holding member for dental floss which is mounted on the holding member and can be replaced. With a change in the angle of the holding member for dental floss by virtue of the locating member it is easy for the user to clean up dirts at the spaces between the teeth in deep cavity of the mouth so as to assure oral hygiene.