Abstract: An analysis filter bank corresponding to multiple sub-bands, which performs frequency-division filtering on an input signal to generate multiple sub-band signals, the analysis filter bank comprising: a sub-band response pre-compensator which performs a linear filtering on the input signal to generate a response pre-compensated signal, multiple sub-filters with different central frequencies, which perform complex-type first-order infinite impulse response filtering respectively on the response pre-compensated signal to generate multiple sub-filter signals, and multiple binomially-combining and rotating devices based on a set of binomial weights, each of which performs a weighted summation on at least two of the sub-filter signals with the set of binomial weights, and rotates a weighted-summation result with a rotating phase according to a corresponding sub-band central frequency to generate one of the sub-band signals, wherein the at least two of the sub-filter signals are generated by at least two of the sub-

Abstract: An analysis filter bank corresponding to a plurality of sub-bands, comprising: multiple sub-filters with different center frequencies which perform multiple complex-type first-order infinite impulse response filtering operations on an audio input signal to generate multiple sub-filter signals; a first set of binomial combiners, each of which performs a weighted-sum operation on a first number of the sub-filter signals with a first set of binomial weights to generate one of multiple sub-band signals; a second set of binomial combiners, each of which performs a weighted-sum operation on a second number of the sub-filter signals with a second set of binomial weights to generate one of multiple lower sub-band-edge signals or one of multiple higher sub-band-edge signals; and multiple envelope detection with decimation devices, which perform multiple envelope detection with decimation operations on the sub-band signals, the lower sub-band-edge signals, and the higher sub-band-edge signals to generate multiple fine

Abstract: An analysis filter bank corresponding to a plurality of sub-bands, comprising: multiple sub-filters with different center frequencies which perform multiple complex-type first-order infinite impulse response filtering operations on an audio input signal to generate multiple sub-filter signals; a first set of binomial combiners, each of which performs a weighted-sum operation on a first number of the sub-filter signals with a first set of binomial weights to generate one of multiple sub-band signals; a second set of binomial combiners, each of which performs a weighted-sum operation on a second number of the sub-filter signals with a second set of binomial weights to generate one of multiple lower sub-band-edge signals or one of multiple higher sub-band-edge signals; and multiple envelope detection with decimation devices, which perform multiple envelope detection with decimation operations on the sub-band signals, the lower sub-band-edge signals, and the higher sub-band-edge signals to generate multiple fine

Abstract: An analysis filter bank corresponding to multiple sub-bands, which performs frequency-division filtering on an input signal to generate multiple sub-band signals, the analysis filter bank comprising: a sub-band response pre-compensator which performs a linear filtering on the input signal to generate a response pre-compensated signal, multiple sub-filters with different central frequencies, which perform complex-type first-order infinite impulse response filtering respectively on the response pre-compensated signal to generate multiple sub-filter signals, and multiple binomially-combining and rotating devices based on a set of binomial weights, each of which performs a weighted summation on at least two of the sub-filter signals with the set of binomial weights, and rotates a weighted-summation result with a rotating phase according to a corresponding sub-band central frequency to generate one of the sub-band signals, wherein the at least two of the sub-filter signals are generated by at least two of the sub-

Abstract: A joint spectral gain adaption module, which comprises: an aided-ear loudness model, wherein an aided-ear loudness spectrum is obtained by performing computations on an aided-ear threshold elevation profile and a spectrum selected from the group consisting of an input spectrum and a first spectrum derived from the input spectrum; a bare-ear loudness model, wherein a bare-ear loudness spectrum is obtained by performing computations on a bare-ear threshold elevation profile, and a modified spectrum previously obtained; and a spectrum shaping sub-module, wherein the modified spectrum previously obtained is passed to the bare-ear loudness model as an input, and a modified spectrum and a linear spectral gain vector are obtained by performing computations on the input spectrum, the bare-ear loudness spectrum, and a loudness spectrum selected from the group consisting of the aided-ear loudness spectrum and a first loudness spectrum derived from the aided-ear loudness spectrum.

Abstract: A joint spectral gain adaption module, which comprises: an aided-ear loudness model, wherein an aided-ear loudness spectrum is obtained by performing computations on an aided-ear threshold elevation profile and a spectrum selected from the group consisting of an input spectrum and a first spectrum derived from the input spectrum; a bare-ear loudness model, wherein a bare-ear loudness spectrum is obtained by performing computations on a bare-ear threshold elevation profile, and a modified spectrum previously obtained; and a spectrum shaping sub-module, wherein the modified spectrum previously obtained is passed to the bare-ear loudness model as an input, and a modified spectrum and a linear spectral gain vector are obtained by performing computations on the input spectrum, the bare-ear loudness spectrum, and a loudness spectrum selected from the group consisting of the aided-ear loudness spectrum and a first loudness spectrum derived from the aided-ear loudness spectrum.

Abstract: A semiconductor chip comprising: an internal clock circuit for generating an internal clock signal; a first phase shift device for shifting the phase of an external clock signal and outputting a phase shifting clock signal; a multiplexer, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad, for outputting the first clock signal; and a controllable pad. The controllable pad is controlled to selectively act as an input pad for receiving the external signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.

Abstract: A semiconductor chip comprising: an internal clock circuit for generating an internal clock signal; a first phase shift device for shifting the phase of an external clock signal and outputting a phase shifting clock signal; a multiplexer, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad, for outputting the first clock signal; and a controllable pad. The controllable pad is controlled to selectively act as an input pad for receiving the external signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.

Abstract: A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal.

Abstract: A television signal processing device and a television signal processing method are proposed according to embodiments of the present invention, wherein the television signal processing device includes a first signal processing unit, a television demodulator, and a second signal processing unit. The first signal processing unit performs a first signal processing operation upon a television signal according to a feedback signal to reduce distortion of the television signal and accordingly generate a processed television signal. The television demodulator is coupled to the first signal processing unit for receiving the processed television signal, and demodulating the processed television signal to generate a demodulated television signal.

Abstract: Apparatuses and methods for scanning channels in a television signal receiver. The apparatuses generally include a first acquisition circuit, a second acquisition circuit, and a controller. The first acquisition circuit is generally configured to determine, during a first time period, whether a selected radio frequency channel has a first format and to produce a first acquisition indicator in response thereto. The second acquisition circuit is generally configured to determine, during a second time period overlapping the first time period, whether the selected radio frequency channel has a second format and to produce a second acquisition indicator in response thereto. The controller is generally configured to scan a plurality of radio frequency channels by operating the first acquisition circuit and the second acquisition circuit for each one of the plurality of radio frequency channels. Embodiments advantageously provides for faster scanning and acquisition of television signals in a mixed-format (e.g.

Abstract: A television signal receiver comprises: a tuner, an optional IF conditioner, an IF distortion canceller, and an IF demodulator. The tuner selects one channel from a radio frequency television signal to generate an intermediate frequency signal. The IF conditioner outputs an IF conditioned signal. The IF distortion canceller cancels a signal distortion in the IF signal or the IF conditioned signal to generate an IF distortion-cancelled signal. The IF demodulator demodulates the IF distortion-cancelled signal to output a baseband signal.

Abstract: A television signal processing device and a television signal processing method are proposed according to embodiments of the present invention, wherein the television signal processing device includes a first signal processing unit, a television demodulator, and a second signal processing unit. The first signal processing unit performs a first signal processing operation upon a television signal according to a feedback signal to reduce distortion of the television signal and accordingly generate a processed television signal. The television demodulator is coupled to the first signal processing unit for receiving the processed television signal, and demodulating the processed television signal to generate a demodulated television signal.

Abstract: A digital communication device is provided for decoding a data stream to generate a receiver output. In the digital communication device, a burst error detector determines burst noise locations corresponding to the data stream according to an error-check equation and accordingly generates a burst error indicator. Thereafter, an inner decoder decodes the data stream to generate an inner decoded stream, comprising an erasure marker for performing an erasure marking process on the inner decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the inner decoded stream. An outer decoder then decodes the inner decoded stream with reference to the erasure indicator to generate the receiver output.

Abstract: A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal.

Abstract: A digitized analog television signal processing system is disclosed, comprising an analog-to-digital converter, a demodulation unit, a decoding unit, and a control unit. The analog-to-digital converter samples a television signal comprising a video signal. The demodulation unit demodulates the video signal. The decoding unit decodes the demodulated video signal. The control unit adjusts the demodulation unit according to a signal quality indicator generated during and/or after the decoding of the decoding unit.

Abstract: A digitizer includes an analog to digital converter (ADC), a sampling frequency generator, and a controller. The ADC samples an IF signal to generate a digital signal. The sampling frequency generator is connected to the ADC and provides a sampling clock of variable frequency to the ADC. The controller is connected to the sampling frequency generator and determines frequency of the sampling clock.

Abstract: An equalization system used in a communication receiver has multiple equalization stages. A front equalizer supplies equalization output to a feed back filter in a rear equalizer to speed initialization of the rear equalizer. In addition, the rear equalizer supplies decision output to the front equalizer to estimate errors so as to provide more accurate tap coefficient adjustments. Both the front equalizer and the rear equalizer can be implemented with iterative equalizers to further enhance equalization performance.

Abstract: A method and an apparatus for calculating an error metric in a digital communication receiver. In the receiver, an input data stream is used to generate at least one input bit stream. The combinational logic unit performs an error-check operation on delayed and current bits of the input bit stream using a polynomial error-check equation previously determined. Finally, an accumulator is used to accumulate a number of trials with respect to the error check operation and generates a nominal error-check number based on the number of the correct trials.

Abstract: An apparatus for generating a detected punctured position in punctured convolutional codes. A delay line circuit has a plurality of delay elements connected in series, storing a finite sequence of an input bit stream. A logic gate circuit, coupled to outputs of a part of the delay elements of the delay line circuit in accordance with a parity check polynomial, performs a logic operation to output a number stream. The number stream is accumulated for possible punctured positions and the one of the possible punctured positions with a minimal accumulated number is selected and determined as the detected punctured position.