Patents by Inventor Ming-Lung Cheng

Ming-Lung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250040201
    Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The structure also includes a first gate structure wrapping around the first nanostructures. The structure also includes a first source/drain epitaxial structure formed beside the first nanostructures. The structure also includes a first inner spacer between the first gate structure and the first source/drain epitaxial structure. The structure also includes second nanostructures formed over the first nanostructure. The structure also includes a second gate structure wrapping around the second nanostructures. The structure also includes a second source/drain epitaxial structure formed beside the second nanostructures. The structure also includes a second inner spacer between the second gate structure and the second source/drain epitaxial structure. A sidewall of the second inner spacer is spaced apart from a sidewall of the first inner spacer when viewed from above.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Shuan LI, Ming-Lung CHENG
  • Patent number: 12191370
    Abstract: A method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and being alternatingly disposed in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess, and forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. The insulation layer is above the base epitaxial layer and above a bottommost channel layer.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Yu Lai, Wei-Yang Lee, Ming-Lung Cheng, Chia-Pin Lin, Yuan-Ching Peng
  • Patent number: 12166071
    Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ko-Cheng Liu, Ming-Shuan Li, Ming-Lung Cheng, Chang-Miao Liu
  • Publication number: 20240395902
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
  • Patent number: 12154946
    Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The semiconductor device structure also includes a first gate structure wrapping around the first nanostructures. The semiconductor device structure also includes a first source/drain epitaxial structure formed beside the first nanostructures. The semiconductor device structure further includes a first inner spacer extending from the first gate structure to the first source/drain epitaxial structure by a first distance. The semiconductor device structure also includes second nanostructures formed over the first nanostructures. The semiconductor device structure further includes a second gate structure wrapping around the second nanostructures. The semiconductor device structure also includes a second source/drain epitaxial structure formed beside the second nanostructures.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Shuan Li, Ming-Lung Cheng
  • Publication number: 20240379813
    Abstract: A semiconductor structure includes a substrate, a semiconductor fin-shaped structure protruding from the substrate and extending lengthwise along a first direction, an isolation feature disposed over the substrate and adjacent to the semiconductor fin-shaped structure and extending lengthwise along the first direction, a metal gate stack disposed over a channel region of the semiconductor fin-shaped structure and extending lengthwise along a second direction perpendicular to the first direction, a gate spacer disposed along a sidewall of the metal gate stack and along a sidewall of the semiconductor fin-shaped structure, a source/drain feature disposed over a source/drain region of the semiconductor fin-shaped structure and adjacent to the metal gate stack, a dielectric layer disposed over the source/drain feature, and an air gap disposed between the gate spacer and the dielectric layer along the first direction and wrapping around the semiconductor fin-shaped structure.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
  • Publication number: 20240379816
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (APT) feature in the active region.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Ko-Cheng Liu, Chang-Miao Liu, Ming-Lung Cheng
  • Publication number: 20240379744
    Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Ko-Cheng Liu, Ming-Shuan Li, Ming-Lung Cheng, Chang-Miao Liu
  • Patent number: 12142668
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
  • Publication number: 20230395679
    Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a dielectric feature disposed directly on the substrate and in direct contact with a portion of the vertical stack of channel members, and a source/drain feature disposed directly on the dielectric feature and electrically coupled to a remaining portion of the vertical stack of channel members.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: Ming-Lung Cheng, Huang-Hsuan Lin, Chih Chieh Yeh
  • Patent number: 11837631
    Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
  • Publication number: 20230387198
    Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
  • Publication number: 20230378320
    Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing an epitaxial feature in the recess to fully covers an end of the semiconductor fin that is otherwise exposed in the recess, trimming the epitaxial feature to reduce a width of the epitaxial feature to expose again a portion of the end of the semiconductor fin in the recess, depositing a dielectric layer on the epitaxial feature and in physical contact with the exposed portion of the end of the semiconductor fin, and replacing the dummy gate structure with a metal gate structure.
    Type: Application
    Filed: March 9, 2023
    Publication date: November 23, 2023
    Inventors: Chun-Fai Cheng, Chang-Miao Liu, Ming-Lung Cheng
  • Patent number: 11810827
    Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Lung Cheng, Yen-Chun Lin, Da-Wen Lin
  • Publication number: 20230352530
    Abstract: The method includes receiving a semiconductor workpiece having active regions extending above a top surface of a semiconductor substrate, forming first dielectric features on first opposing sidewalls of the active regions across a first direction, forming second dielectric features extending between opposing sidewalls of the first dielectric features, and etching portions of the active region to form source/drain trenches. The source/drain trenches expose second opposing sidewalls of the active region. The method further includes recessing the first dielectric features and forming source/drain features in the source/drain trenches and on the exposed second opposing sidewalls of the active region. The source/drain features are partially formed on top surfaces of the first dielectric features.
    Type: Application
    Filed: June 26, 2023
    Publication date: November 2, 2023
    Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
  • Publication number: 20230335616
    Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing fin-shaped active regions protruding from a substrate, forming cladding layers extending along sidewalls of the fin-shaped active regions, forming a dielectric feature over the substrate to fill space between two adjacent cladding layers, forming a gate structure over channel regions of the fin-shaped active regions and over a first portion of the cladding layers, performing an etching process to remove a second portion of the cladding layers not covered by the gate structure to form sidewall spacer trenches, forming a dielectric spacer in each of the sidewall spacer trenches, and after the forming of the dielectric spacers, forming source/drain features.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 19, 2023
    Inventors: Chun-Fai Cheng, Chang-Miao Liu, Ming-Lung Cheng
  • Publication number: 20230335600
    Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a work function layer surrounding the nanostructures. The method also includes forming spacers over opposite sides of the work function layer. The method also includes forming a first metal layer over the work function layer and sidewalls of the spacers. The method also includes forming a second metal layer surrounded by the first metal layer. The method also includes etching the first metal layer over opposite sides of the second metal layer. The method also includes forming a cap layer over a top surface and a sidewall of the second metal layer.
    Type: Application
    Filed: April 15, 2022
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Lung CHENG, Huang-Hsuan LIN, Chih-Chieh YEH
  • Publication number: 20230282704
    Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The semiconductor device structure also includes a first gate structure wrapping around the first nanostructures. The semiconductor device structure also includes a first source/drain epitaxial structure formed beside the first nanostructures. The semiconductor device structure further includes a first inner spacer extending from the first gate structure to the first source/drain epitaxial structure by a first distance. The semiconductor device structure also includes second nanostructures formed over the first nanostructures. The semiconductor device structure further includes a second gate structure wrapping around the second nanostructures. The semiconductor device structure also includes a second source/drain epitaxial structure formed beside the second nanostructures.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Shuan LI, Ming-Lung CHENG
  • Publication number: 20230261077
    Abstract: An exemplary device includes a stack of channel layers over a substrate extension, a gate, and an insulation layer. The stack of channel layers extends between a first epitaxial source/drain and a second epitaxial source/drain. The gate surrounds each channel layer of the stack of the channel layers. The insulation layer is over the substrate extension, the gate is between a bottommost channel layer of the stack of channel layers and the insulation layer, and the insulation layer is between the gate and the substrate extension. The insulation layer extends between the first epitaxial source/drain and the second epitaxial source/drain, each of which may include an undoped epitaxial layer. A top surface of the undoped epitaxial layer is below a bottom surface of the bottommost channel layer and/or above a top surface of the insulation layer. The insulation layer may wrap the substrate extension and/or have an air gap therein.
    Type: Application
    Filed: June 6, 2022
    Publication date: August 17, 2023
    Inventors: Ko-Cheng Liu, Chang-Miao Liu, Ming-Lung Cheng
  • Patent number: 11688768
    Abstract: The device includes a semiconductor substrate and a stack of channel layers on the semiconductor substrate. A top surface of a topmost channel layer extends along a first height relative to the substrate surface. A bottom surface of a bottommost channel layer extends along a second height relative to the substrate surface. The device further includes a gate structure that engages with the stack of channel layers and extending along a first direction. Additionally, the device includes a source/drain feature on first sidewall surfaces of the stack of channel layers and on the substrate, where the first sidewall surfaces extends in parallel to the first direction. Moreover, the source/drain feature has a first width along the first direction at the first height and a second width along the first direction at the second height, and wherein the first width is greater than the second width.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu