Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a dielectric feature disposed directly on the substrate and in direct contact with a portion of the vertical stack of channel members, and a source/drain feature disposed directly on the dielectric feature and electrically coupled to a remaining portion of the vertical stack of channel members.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing an epitaxial feature in the recess to fully covers an end of the semiconductor fin that is otherwise exposed in the recess, trimming the epitaxial feature to reduce a width of the epitaxial feature to expose again a portion of the end of the semiconductor fin in the recess, depositing a dielectric layer on the epitaxial feature and in physical contact with the exposed portion of the end of the semiconductor fin, and replacing the dummy gate structure with a metal gate structure.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: The method includes receiving a semiconductor workpiece having active regions extending above a top surface of a semiconductor substrate, forming first dielectric features on first opposing sidewalls of the active regions across a first direction, forming second dielectric features extending between opposing sidewalls of the first dielectric features, and etching portions of the active region to form source/drain trenches. The source/drain trenches expose second opposing sidewalls of the active region. The method further includes recessing the first dielectric features and forming source/drain features in the source/drain trenches and on the exposed second opposing sidewalls of the active region. The source/drain features are partially formed on top surfaces of the first dielectric features.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a work function layer surrounding the nanostructures. The method also includes forming spacers over opposite sides of the work function layer. The method also includes forming a first metal layer over the work function layer and sidewalls of the spacers. The method also includes forming a second metal layer surrounded by the first metal layer. The method also includes etching the first metal layer over opposite sides of the second metal layer. The method also includes forming a cap layer over a top surface and a sidewall of the second metal layer.

Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing fin-shaped active regions protruding from a substrate, forming cladding layers extending along sidewalls of the fin-shaped active regions, forming a dielectric feature over the substrate to fill space between two adjacent cladding layers, forming a gate structure over channel regions of the fin-shaped active regions and over a first portion of the cladding layers, performing an etching process to remove a second portion of the cladding layers not covered by the gate structure to form sidewall spacer trenches, forming a dielectric spacer in each of the sidewall spacer trenches, and after the forming of the dielectric spacers, forming source/drain features.

Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The semiconductor device structure also includes a first gate structure wrapping around the first nanostructures. The semiconductor device structure also includes a first source/drain epitaxial structure formed beside the first nanostructures. The semiconductor device structure further includes a first inner spacer extending from the first gate structure to the first source/drain epitaxial structure by a first distance. The semiconductor device structure also includes second nanostructures formed over the first nanostructures. The semiconductor device structure further includes a second gate structure wrapping around the second nanostructures. The semiconductor device structure also includes a second source/drain epitaxial structure formed beside the second nanostructures.

Abstract: An exemplary device includes a stack of channel layers over a substrate extension, a gate, and an insulation layer. The stack of channel layers extends between a first epitaxial source/drain and a second epitaxial source/drain. The gate surrounds each channel layer of the stack of the channel layers. The insulation layer is over the substrate extension, the gate is between a bottommost channel layer of the stack of channel layers and the insulation layer, and the insulation layer is between the gate and the substrate extension. The insulation layer extends between the first epitaxial source/drain and the second epitaxial source/drain, each of which may include an undoped epitaxial layer. A top surface of the undoped epitaxial layer is below a bottom surface of the bottommost channel layer and/or above a top surface of the insulation layer. The insulation layer may wrap the substrate extension and/or have an air gap therein.

Abstract: The device includes a semiconductor substrate and a stack of channel layers on the semiconductor substrate. A top surface of a topmost channel layer extends along a first height relative to the substrate surface. A bottom surface of a bottommost channel layer extends along a second height relative to the substrate surface. The device further includes a gate structure that engages with the stack of channel layers and extending along a first direction. Additionally, the device includes a source/drain feature on first sidewall surfaces of the stack of channel layers and on the substrate, where the first sidewall surfaces extends in parallel to the first direction. Moreover, the source/drain feature has a first width along the first direction at the first height and a second width along the first direction at the second height, and wherein the first width is greater than the second width.

Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The structure also includes a first gate structure wrapped around the first nanostructures. The structure also includes first source/drain epitaxial structures formed over opposite sides of the first nanostructures. The structure also includes second nanostructures formed over the first nanostructure. The structure also includes a second gate structure wrapped around the second nanostructures. The structure also includes second source/drain epitaxial structures formed over opposite sides of the second nanostructures. The first gate structure and the second gate structure have different conductivity types, and the Ge concentration of the first nanostructures and the Ge concentration of the second nanostructures are different.

Abstract: A method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and being alternatingly disposed in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess, and forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. The insulation layer is above the base epitaxial layer and above a bottommost channel layer.

Abstract: A method includes providing a structure having two fins extending from a substrate and an isolation structure adjacent to lower portions of the fins; forming a cladding layer over the isolation structure and over top and sidewalls of the fins; recessing the isolation structure using the cladding layer as an etch mask to expose the substrate; after the recessing of the isolation structure, depositing a seal layer over the substrate, the isolation structure, and the cladding layer; forming a sacrificial plug over the seal layer and between the two fins; and depositing a dielectric top cover over the sacrificial plug and laterally between the two fins.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (APT) feature in the active region.

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

Abstract: A method includes providing a semiconductor structure including a device fin protruding from a substrate, forming a dummy gate stack over the device fin, forming a first spacer over the device fin and the dummy gate stack, forming a second spacer over the first spacer, forming a dielectric feature adjacent to the second spacer, and replacing the dummy gate stack with a metal gate stack. Thereafter, the method removes the second spacer, thereby forming an air gap between the first spacer and the dielectric feature and wrapping around the device fin. The method then forms a sealing layer over the first spacer and the dielectric feature, thereby sealing the air gap.

Abstract: The device includes a semiconductor substrate and a stack of channel layers on the semiconductor substrate. A top surface of a topmost channel layer extends along a first height relative to the substrate surface. A bottom surface of a bottommost channel layer extends along a second height relative to the substrate surface. The device further includes a gate structure that engages with the stack of channel layers and extending along a first direction. Additionally, the device includes a source/drain feature on first sidewall surfaces of the stack of channel layers and on the substrate, where the first sidewall surfaces extends in parallel to the first direction. Moreover, the source/drain feature has a first width along the first direction at the first height and a second width along the first direction at the second height, and wherein the first width is greater than the second width.

Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The structure also includes a first gate structure wrapped around the first nanostructures. The structure also includes first source/drain epitaxial structures formed over opposite sides of the first nanostructures. The structure also includes second nanostructures formed over the first nanostructure. The structure also includes a second gate structure wrapped around the second nanostructures. The structure also includes second source/drain epitaxial structures formed over opposite sides of the second nanostructures. The first gate structure and the second gate structure have different conductivity types, and the Ge concentration of the first nanostructures and the Ge concentration of the second nanostructures are different.