Patents by Inventor Ming-Sheng Tung

Ming-Sheng Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9525424
    Abstract: Disclosed is a method for enhancing temperature efficiency, used to enhance a temperature efficiency resulted from temperature changes in regard to an oscillating period of an oscillator. The method for enhancing temperature efficiency comprises the steps as follows: generating a PTAT current by using a bandgap circuit; generating a CTAT current by using a bandgap circuit; generating an output current, wherein the output current equals to PTAT current minus CTAT current; and providing the output current to an oscillator for generating an oscillating frequency.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: December 20, 2016
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Ming-Sheng Tung
  • Publication number: 20160315624
    Abstract: Disclosed is a method for enhancing temperature efficiency, used to enhance a temperature efficiency resulted from temperature changes in regard to an oscillating period of an oscillator. The method for enhancing temperature efficiency comprises the steps as follows: generating a PTAT current by using a bandgap circuit; generating a CTAT current by using a bandgap circuit; generating an output current, wherein the output current equals to PTAT current minus CTAT current; and providing the output current to an oscillator for generating an oscillating frequency.
    Type: Application
    Filed: April 22, 2015
    Publication date: October 27, 2016
    Inventor: MING-SHENG TUNG
  • Patent number: 9300276
    Abstract: An oscillation control circuit for a ring oscillator includes a bandgap reference circuit and an oscillation frequency control circuit. The bandgap reference circuit is arranged for generating a bandgap reference signal by mirroring a proportional-to-absolute-temperature current. The oscillation frequency control circuit is coupled to the bandgap reference circuit, and is arranged for biasing the ring oscillator according to the bandgap reference signal. When the ring oscillator has a plurality of stages, the oscillation frequency control circuit includes one current source and a plurality of current mirrors for biasing the plurality of stages of the ring oscillator, respectively.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: March 29, 2016
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Sheng Tung
  • Publication number: 20140191814
    Abstract: An oscillation control circuit for a ring oscillator includes a bandgap reference circuit and an oscillation frequency control circuit. The bandgap reference circuit is arranged for generating a bandgap reference signal by mirroring a proportional-to-absolute-temperature current. The oscillation frequency control circuit is coupled to the bandgap reference circuit, and is arranged for biasing the ring oscillator according to the bandgap reference signal. When the ring oscillator has a plurality of stages, the oscillation frequency control circuit includes one current source and a plurality of current mirrors for biasing the plurality of stages of the ring oscillator, respectively.
    Type: Application
    Filed: January 8, 2013
    Publication date: July 10, 2014
    Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Ming-Sheng Tung
  • Patent number: 8698479
    Abstract: A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 15, 2014
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Sheng Tung
  • Patent number: 8599633
    Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.
    Type: Grant
    Filed: May 6, 2012
    Date of Patent: December 3, 2013
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Sheng Tung
  • Publication number: 20130307515
    Abstract: The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.
    Type: Application
    Filed: May 21, 2012
    Publication date: November 21, 2013
    Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Ming-Sheng Tung
  • Publication number: 20130294178
    Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.
    Type: Application
    Filed: May 6, 2012
    Publication date: November 7, 2013
    Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: MING-SHENG TUNG
  • Patent number: 8575912
    Abstract: The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: November 5, 2013
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Sheng Tung
  • Publication number: 20130257396
    Abstract: A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventor: Ming-Sheng Tung
  • Patent number: 7427569
    Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: September 23, 2008
    Assignee: ProMOS Technologies Inc.
    Inventors: Tza-Hao Wang, Jin-Yang Huang, Hung-Kwei Liao, Ming-Sheng Tung
  • Patent number: 7320912
    Abstract: A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: January 22, 2008
    Assignee: PROMOS Technologies Inc.
    Inventors: Yueh-Chuan Lee, Ming-Sheng Tung
  • Publication number: 20070166979
    Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.
    Type: Application
    Filed: February 23, 2006
    Publication date: July 19, 2007
    Inventors: Tza-Hao Wang, Jin-Yang Huang, Hung-Kwei Liao, Ming-Sheng Tung
  • Publication number: 20070090409
    Abstract: The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor device also comprises a barrier layer, which is located in the memory array area and the periphery circuit area, an undoped oxide barrier, which is located on the barrier layer in the periphery circuit area, and a boron-containing silicate glass, which is located on the barrier layer in the memory array area and on the undoped oxide barrier in the periphery circuit area.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Chia-Shun Hsiao, Ming-Sheng Tung, Hong-Ming Chen, Ching-Hsien Huang
  • Publication number: 20070093014
    Abstract: The present invention provides a method for preventing doped boron in a dielectric layer from diffusing into a substrate. First, at least one gate is formed on a periphery circuit area and a memory array area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. Then, a barrier layer is formed on the memory array area and the periphery circuit area, and an undoped oxide barrier is formed on the periphery circuit area. Finally, a silicate glass containing boron is deposited on the memory array area and the periphery circuit area.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Chia-Shun Hsiao, Ming-Sheng Tung, Hong-Ming Chen, Ching-Hsien Huang
  • Publication number: 20060255388
    Abstract: A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.
    Type: Application
    Filed: May 10, 2005
    Publication date: November 16, 2006
    Inventors: Yueh-Chuan Lee, Ming-Sheng Tung
  • Publication number: 20060128157
    Abstract: A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
    Type: Application
    Filed: January 25, 2006
    Publication date: June 15, 2006
    Inventors: Yueh-Chuan Lee, Ming-Sheng Tung
  • Patent number: 7034354
    Abstract: A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: April 25, 2006
    Assignee: Promos Technologies Inc.
    Inventors: Yueh-Chuan Lee, Ming-Sheng Tung
  • Publication number: 20050127453
    Abstract: A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.
    Type: Application
    Filed: January 21, 2005
    Publication date: June 16, 2005
    Applicant: Promos Technologies, Inc.
    Inventors: Ming-Sheng Tung, Yueh-Chuan Lee
  • Publication number: 20050106844
    Abstract: Ions are implanted into a substrate, using a gate and its sidewall liner on the substrate as the mask, to form a source/drain region in the substrate beneath the liner and adjacent to the two sides of the gate. The liner is etched to reduce its thickness. Then, ions are implanted into the substrate to form a halo doped region surrounding the source/drain region. The halo doped region is closer to the MOSFET channel region and overlaps less with the source/drain region. Therefore, the device threshold voltage can be sustained and the junction leakage can also be minimized.
    Type: Application
    Filed: February 27, 2004
    Publication date: May 19, 2005
    Inventors: Ming-Sheng Tung, Yueh-Chuan Lee, Fang-Yu Yeh, Chi Lin