Patents by Inventor Ming-Sheng Tung
Ming-Sheng Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11574684Abstract: The present invention relates to a dynamic random access memory and a programming method therefor with two stages. In a first stage, a capacitor of a memory cell of the dynamic random access memory is broken down, so that the dynamic random access memory becomes a one-time programmable memory. In a second stage, a resistance of the capacitor that is broken down is reduced, so that state data of the memory cell can be more easily interpreted.Type: GrantFiled: April 26, 2021Date of Patent: February 7, 2023Assignee: NS Poles Technology Corp.Inventors: Chao Yang Chen, Ming Sheng Tung
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Publication number: 20220215884Abstract: The present invention relates to a dynamic random access memory and a programming method therefor with two stages. In a first stage, a capacitor of a memory cell of the dynamic random access memory is broken down, so that the dynamic random access memory becomes a one-time programmable memory. In a second stage, a resistance of the capacitor that is broken down is reduced, so that state data of the memory cell can be more easily interpreted.Type: ApplicationFiled: April 26, 2021Publication date: July 7, 2022Inventors: CHAO YANG CHEN, MING SHENG TUNG
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Publication number: 20220013158Abstract: A magnetoresistive random access memory (MRAM) includes a plurality of input/output units. Each input/output units can read and write memory cells simultaneously. So a read/write column to column delay time (tCCD) of the MRAM is equal to or shorter than a read/write column to column delay time of a dynamic random access memory (DRAM). Consequently, a data-rate of the MRAM is equal to or shorter than a data-rate of the DRAM.Type: ApplicationFiled: September 17, 2020Publication date: January 13, 2022Inventors: MING SHENG TUNG, WEN CHIN LIN
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Patent number: 11222677Abstract: A magnetoresistive random access memory (MRAM) includes a plurality of input/output units. Each input/output units can read and write memory cells simultaneously. So a read/write column to column delay time (tCCD) of the MRAM is equal to or shorter than a read/write column to column delay time of a dynamic random access memory (DRAM). Consequently, a data-rate of the MRAM is equal to or shorter than a data-rate of the DRAM.Type: GrantFiled: September 17, 2020Date of Patent: January 11, 2022Assignee: NS Poles Technology Corp.Inventors: Ming Sheng Tung, Wen Chin Lin
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Patent number: 9525424Abstract: Disclosed is a method for enhancing temperature efficiency, used to enhance a temperature efficiency resulted from temperature changes in regard to an oscillating period of an oscillator. The method for enhancing temperature efficiency comprises the steps as follows: generating a PTAT current by using a bandgap circuit; generating a CTAT current by using a bandgap circuit; generating an output current, wherein the output current equals to PTAT current minus CTAT current; and providing the output current to an oscillator for generating an oscillating frequency.Type: GrantFiled: April 22, 2015Date of Patent: December 20, 2016Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Ming-Sheng Tung
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Publication number: 20160315624Abstract: Disclosed is a method for enhancing temperature efficiency, used to enhance a temperature efficiency resulted from temperature changes in regard to an oscillating period of an oscillator. The method for enhancing temperature efficiency comprises the steps as follows: generating a PTAT current by using a bandgap circuit; generating a CTAT current by using a bandgap circuit; generating an output current, wherein the output current equals to PTAT current minus CTAT current; and providing the output current to an oscillator for generating an oscillating frequency.Type: ApplicationFiled: April 22, 2015Publication date: October 27, 2016Inventor: MING-SHENG TUNG
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Patent number: 9300276Abstract: An oscillation control circuit for a ring oscillator includes a bandgap reference circuit and an oscillation frequency control circuit. The bandgap reference circuit is arranged for generating a bandgap reference signal by mirroring a proportional-to-absolute-temperature current. The oscillation frequency control circuit is coupled to the bandgap reference circuit, and is arranged for biasing the ring oscillator according to the bandgap reference signal. When the ring oscillator has a plurality of stages, the oscillation frequency control circuit includes one current source and a plurality of current mirrors for biasing the plurality of stages of the ring oscillator, respectively.Type: GrantFiled: January 8, 2013Date of Patent: March 29, 2016Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Ming-Sheng Tung
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Publication number: 20140191814Abstract: An oscillation control circuit for a ring oscillator includes a bandgap reference circuit and an oscillation frequency control circuit. The bandgap reference circuit is arranged for generating a bandgap reference signal by mirroring a proportional-to-absolute-temperature current. The oscillation frequency control circuit is coupled to the bandgap reference circuit, and is arranged for biasing the ring oscillator according to the bandgap reference signal. When the ring oscillator has a plurality of stages, the oscillation frequency control circuit includes one current source and a plurality of current mirrors for biasing the plurality of stages of the ring oscillator, respectively.Type: ApplicationFiled: January 8, 2013Publication date: July 10, 2014Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Ming-Sheng Tung
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Patent number: 8698479Abstract: A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.Type: GrantFiled: March 30, 2012Date of Patent: April 15, 2014Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Ming-Sheng Tung
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Patent number: 8599633Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.Type: GrantFiled: May 6, 2012Date of Patent: December 3, 2013Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Ming-Sheng Tung
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Publication number: 20130307515Abstract: The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.Type: ApplicationFiled: May 21, 2012Publication date: November 21, 2013Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Ming-Sheng Tung
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Publication number: 20130294178Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.Type: ApplicationFiled: May 6, 2012Publication date: November 7, 2013Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: MING-SHENG TUNG
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Patent number: 8575912Abstract: The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.Type: GrantFiled: May 21, 2012Date of Patent: November 5, 2013Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Ming-Sheng Tung
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Publication number: 20130257396Abstract: A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Inventor: Ming-Sheng Tung
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Patent number: 7427569Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.Type: GrantFiled: February 23, 2006Date of Patent: September 23, 2008Assignee: ProMOS Technologies Inc.Inventors: Tza-Hao Wang, Jin-Yang Huang, Hung-Kwei Liao, Ming-Sheng Tung
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Patent number: 7320912Abstract: A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.Type: GrantFiled: May 10, 2005Date of Patent: January 22, 2008Assignee: PROMOS Technologies Inc.Inventors: Yueh-Chuan Lee, Ming-Sheng Tung
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Publication number: 20070166979Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.Type: ApplicationFiled: February 23, 2006Publication date: July 19, 2007Inventors: Tza-Hao Wang, Jin-Yang Huang, Hung-Kwei Liao, Ming-Sheng Tung
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Publication number: 20070090409Abstract: The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor device also comprises a barrier layer, which is located in the memory array area and the periphery circuit area, an undoped oxide barrier, which is located on the barrier layer in the periphery circuit area, and a boron-containing silicate glass, which is located on the barrier layer in the memory array area and on the undoped oxide barrier in the periphery circuit area.Type: ApplicationFiled: October 26, 2005Publication date: April 26, 2007Inventors: Chia-Shun Hsiao, Ming-Sheng Tung, Hong-Ming Chen, Ching-Hsien Huang
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Publication number: 20070093014Abstract: The present invention provides a method for preventing doped boron in a dielectric layer from diffusing into a substrate. First, at least one gate is formed on a periphery circuit area and a memory array area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. Then, a barrier layer is formed on the memory array area and the periphery circuit area, and an undoped oxide barrier is formed on the periphery circuit area. Finally, a silicate glass containing boron is deposited on the memory array area and the periphery circuit area.Type: ApplicationFiled: October 26, 2005Publication date: April 26, 2007Inventors: Chia-Shun Hsiao, Ming-Sheng Tung, Hong-Ming Chen, Ching-Hsien Huang
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Publication number: 20060255388Abstract: A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.Type: ApplicationFiled: May 10, 2005Publication date: November 16, 2006Inventors: Yueh-Chuan Lee, Ming-Sheng Tung