Patents by Inventor Ming-Shiang LIN
Ming-Shiang LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103480Abstract: A controller for controlling an electric motor module equipped with incremental encoder and operation method thereof are provided. The controller includes a quadruple frequency circuit, a driver circuit, a non-volatile memory (NVM) and a multi-phase control circuit. The multi-phase control circuit can perform multi-phase control with aid of the NVM, for example: reading an offset counter value from the NVM; executing an initial angle estimation procedure, generating an initial counter value according to an estimated initial angle and the offset counter value, and starting utilizing the driver circuit to directly control the electric motor to start with the estimated initial angle and utilizing a counter to perform counting operations; calculating a counter value error and clear the current counter value to be zero; and performing compensation corresponding to a predetermined compensation times count according to the counter value error, respectively, to control the rotor to reach a target angle.Type: ApplicationFiled: August 11, 2023Publication date: March 28, 2024Applicant: Artery Technology CompanyInventors: Ming-Tsan Lin, Yi-Shiang Ouyang, Zi-Xuan Huang
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Patent number: 11942380Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.Type: GrantFiled: October 26, 2020Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
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Publication number: 20240072685Abstract: A power converter to supply power to each phase of a three-phase motor includes a booster circuit connected to a DC power supply to boost an input voltage input from the DC power supply in response to a pulse width modulation boosting signal, an inverter connected to the booster circuit and including a three-phase switching circuit including switches, and an output connected to the three-phase switching circuit to supply power to each phase of the three-phase motor, and a controller to output the pulse width modulation boosting signal to the booster circuit and output the pulse width modulation boosting signal to the booster circuit when detecting that the booster circuit is in a boosted state.Type: ApplicationFiled: September 30, 2020Publication date: February 29, 2024Inventors: Ming Tsan LIN, Yi-Shiang OUYANG, Hsin-Chang YU
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Patent number: 11855221Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.Type: GrantFiled: July 27, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Ho, Ming-Shiang Lin, Jin Cai
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Publication number: 20230387310Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Chia-Cheng Ho, Ming-Shiang Lin, Jin Cai
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Publication number: 20230352507Abstract: A plurality of photovoltaic junctions for a subpixel may be formed in a semiconductor substrate. After thinning the backside of the semiconductor substate, at least one transparent refraction structure may be formed on the backside surface of the thinned semiconductor substrate. Each transparent refraction structure has a variable thickness that decreases with a lateral distance from a vertical axis passing through a geometrical center of the second-conductivity-type pillar structures for the subpixel. A subpixel optics assembly including an optical lens may be formed over the at least one transparent refraction structure. Each transparent refraction structure may reduce the tilt angle of light that propagate downward into the photodetectors, and increases total internal reflection of light and increase the efficiency of the photodetectors.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: Ming-Shiang Lin, Yun-Hao Chen, Kuo-Yu Wu, Tse-Hua Lu
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Patent number: 11749700Abstract: A plurality of photovoltaic junctions for a subpixel may be formed in a semiconductor substrate. After thinning the backside of the semiconductor substrate, at least one transparent refraction structure may be formed on the backside surface of the thinned semiconductor substrate. Each transparent refraction structure has a variable thickness that decreases with a lateral distance from a vertical axis passing through a geometrical center of the second-conductivity-type pillar structures for the subpixel. A subpixel optics assembly including an optical lens may be formed over the at least one transparent refraction structure. Each transparent refraction structure may reduce the tilt angle of light that propagate downward into the photodetectors, and increases total internal reflection of light and increase the efficiency of the photodetectors.Type: GrantFiled: April 16, 2021Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming-Shiang Lin, Yun-Hao Chen, Kuo-Yu Wu, Tse-Hua Lu
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Publication number: 20230017723Abstract: A semiconductor device, a back-side deep trench isolation (BDTI) structure of a semiconductor device, and method of manufacturing a semiconductor structure are provided. The semiconductor device, comprising: a pixel region disposed within a substrate and comprising an image sensing element configured to convert electromagnetic radiation into an electrical signal; and one or more BDTI structures extending from a first-side of the substrate to positions within the substrate; wherein the one or more of BDTI structures comprise one or more ferroelectric materials.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Inventors: MING-SHIANG LIN, TZUNG-YI TSAI, WAN-LIN CHIANG, HONG-PING LUO, KUO-YU WU, TSE-HUA LU
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Patent number: 11522085Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.Type: GrantFiled: October 18, 2019Date of Patent: December 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Cheng Ho, Ming-Shiang Lin, Jin Cai
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Patent number: 11513145Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.Type: GrantFiled: August 3, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yi Peng, Chia-Cheng Ho, Ming-Shiang Lin, Chih-Sheng Chang, Carlos H. Diaz
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Publication number: 20220367678Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
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Publication number: 20220367718Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Chia-Cheng Ho, Ming-Shiang Lin, Jin Cai
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Publication number: 20220302315Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
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Patent number: 11444174Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.Type: GrantFiled: September 5, 2019Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Tai Chang, Tung Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
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Patent number: 11387360Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.Type: GrantFiled: May 14, 2020Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
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Publication number: 20210375970Abstract: A plurality of photovoltaic junctions for a subpixel may be formed in a semiconductor substrate. After thinning the backside of the semiconductor substrate, at least one transparent refraction structure may be formed on the backside surface of the thinned semiconductor substrate. Each transparent refraction structure has a variable thickness that decreases with a lateral distance from a vertical axis passing through a geometrical center of the second-conductivity-type pillar structures for the subpixel. A subpixel optics assembly including an optical lens may be formed over the at least one transparent refraction structure. Each transparent refraction structure may reduce the tilt angle of light that propagate downward into the photodetectors, and increases total internal reflection of light and increase the efficiency of the photodetectors.Type: ApplicationFiled: April 16, 2021Publication date: December 2, 2021Inventors: Ming-Shiang LIN, Yun-Hao CHEN, Kuo-Yu WU, Tse-Hua LU
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Patent number: 11189726Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.Type: GrantFiled: May 14, 2020Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
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Publication number: 20210119050Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Inventors: Chia-Cheng Ho, Ming-Shiang Lin, Jin Cai
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Publication number: 20210057290Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.Type: ApplicationFiled: October 26, 2020Publication date: February 25, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Shiang LIN, Chia-Cheng HO, Chun-Chieh LU, Cheng-Yi PENG, Chih-Sheng CHANG
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Publication number: 20210018544Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.Type: ApplicationFiled: August 3, 2020Publication date: January 21, 2021Inventors: Cheng-Yi PENG, Chia-Cheng HO, Ming-Shiang LIN, Chih-Sheng CHANG, Carlos H. DIAZ