Patents by Inventor Ming-Yi Lee
Ming-Yi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
-
Patent number: 11948837Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fu Yeh, Chin-Lung Chung, Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
-
Publication number: 20240088042Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.Type: ApplicationFiled: January 11, 2023Publication date: March 14, 2024Inventors: SHU-WEI LI, HAN-TANG HUNG, YU-CHEN CHAN, CHIEN-HSIN HO, SHIN-YI YANG, MING-HAN LEE, SHAU-LIN SHUE
-
Publication number: 20240087990Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor package. In one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Shin-Yi YANG, Ming-Han LEE, Shau-Lin SHUE
-
Patent number: 11929326Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.Type: GrantFiled: December 20, 2021Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
-
Publication number: 20240081081Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
-
Publication number: 20240071822Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Lung CHUNG, Shin-Yi YANG, Yu-Chen CHAN, Han-Tang HUNG, Shu-Wei LI, Ming-Han LEE
-
Patent number: 9734572Abstract: The present disclosure provides a method including providing a first image and a second image. The first image is of a substrate having a defect and the second image is of a reference substrate. A difference between the first image and the second image is determined. A simulation model is used to generate a simulation curve corresponding to the difference and the substrate dispositioned based on the simulation curve. In another embodiment, the scan of a substrate is used to generate a statistical process control chart.Type: GrantFiled: February 2, 2015Date of Patent: August 15, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Wei Tien, Chi-Hung Liao, Ming-Yi Lee
-
Patent number: 9449656Abstract: A memory includes a plurality of bit cells. Each bit cell includes a bit line and a storage cell coupled to the bit line. A header PMOS transistor is coupled to the storage cell in each bit cell. The header PMOS transistor is at least partially turned off during a write operation by a header control signal.Type: GrantFiled: May 24, 2013Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Han Huang, Ming-Yi Lee, Chia-En Huang, Fu-An Wu, Jung-Ping Yang, Cheng-Hung Lee
-
Patent number: 9412742Abstract: A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern.Type: GrantFiled: June 10, 2014Date of Patent: August 9, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Kao-Cheng Lin, Ming-Yi Lee, Yen-Huei Chen, Hung-Jen Liao
-
Publication number: 20150357279Abstract: A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern.Type: ApplicationFiled: June 10, 2014Publication date: December 10, 2015Inventors: Hidehiro FUJIWARA, Kao-Cheng LIN, Ming-Yi LEE, Yen-Huei CHEN, Hung-Jen LIAO
-
Publication number: 20150146968Abstract: The present disclosure provides a method including providing a first image and a second image. The first image is of a substrate having a defect and the second image is of a reference substrate. A difference between the first image and the second image is determined. A simulation model is used to generate a simulation curve corresponding to the difference and the substrate dispositioned based on the simulation curve. In another embodiment, the scan of a substrate is used to generate a statistical process control chart.Type: ApplicationFiled: February 2, 2015Publication date: May 28, 2015Inventors: Yao-Wei Tien, Chi-Hung Liao, Ming-Yi Lee
-
Publication number: 20150069585Abstract: A semiconductor device includes a first passivation layer including a first passivation portion and a second passivation portion substantially diametrically opposite the first passivation portion. The semiconductor device includes a first corner of the first passivation portion separated a first distance from a second corner of the second passivation portion. A third corner of the first passivation portion is separated a second distance from a fourth corner of the second passivation portion.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Inventors: Chen Jui-Chun, Ming-Yi Lee, Feng-Chi Chou, Shih-Han Liu
-
Patent number: 8965102Abstract: The present disclosure provides a method including providing a first image and a second image. The first image is of a substrate having a defect and the second image is of a reference substrate. A difference between the first image and the second image is determined. A simulation model is used to generate a simulation curve corresponding to the difference and the substrate dispositioned based on the simulation curve. In another embodiment, the scan of a substrate is used to generate a statistical process control chart.Type: GrantFiled: November 9, 2012Date of Patent: February 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Wei Tien, Chi-Hung Liao, Ming-Yi Lee
-
Publication number: 20140185394Abstract: A memory includes a plurality of bit cells. Each bit cell includes a bit line and a storage cell coupled to the bit line. A header PMOS transistor is coupled to the storage cell in each bit cell. The header PMOS transistor is at least partially turned off during a write operation by a header control signal.Type: ApplicationFiled: May 24, 2013Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Han Huang, Ming-Yi Lee, Chia-En Huang, Fu-An Wu, Jung-Ping Yang, Cheng-Hung Lee
-
Publication number: 20140133736Abstract: The present disclosure provides a method including providing a first image and a second image. The first image is of a substrate having a defect and the second image is of a reference substrate. A difference between the first image and the second image is determined. A simulation model is used to generate a simulation curve corresponding to the difference and the substrate dispositioned based on the simulation curve. In another embodiment, the scan of a substrate is used to generate a statistical process control chart.Type: ApplicationFiled: November 9, 2012Publication date: May 15, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yan-Wei Tien, Chi-Hung Liao, Ming-Yi Lee
-
Patent number: 8665654Abstract: A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.Type: GrantFiled: June 21, 2013Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Chen Cheng, Ming-Yi Lee, Kuo-Hua Pan, Jung-Hsuan Chen, Li-Chun Tien, Cheng Hung Lee, Hung-Jen Liao
-
Publication number: 20130286708Abstract: A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.Type: ApplicationFiled: June 21, 2013Publication date: October 31, 2013Inventors: Hong-Chen CHENG, Ming-Yi LEE, Kuo-Hua PAN, Jung-Hsuan CHEN, Li-Chun TIEN, Cheng Hung LEE, Hung-Jen LIAO
-
Patent number: 8482990Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.Type: GrantFiled: February 11, 2011Date of Patent: July 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Chen Cheng, Ming-Yi Lee, Kuo-Hua Pan, Jung-Hsuan Chen, Li-Chun Tien, Cheng Hung Lee, Hung-Jen Liao
-
Publication number: 20120206953Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.Type: ApplicationFiled: February 11, 2011Publication date: August 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hong-Chen CHENG, Ming-Yi LEE, Kuo-Hua PAN, Jung-Hsuan CHEN, Li-Chun TIEN, Cheng Hung LEE, Hung-Jen LIAO