Abstract: A releasable nut-free C-clip secured pipe fitting includes a pipe to be jointed, a C-clip, a sealing ring, and a pipe fitting. The pipe has a jointed end forming a circumferential groove for receiving the C-clip. The C-clip is a ring like member having an opening, which allows for expansion and contraction of the C-clip so as to allow the C-clip to be disposed in a converging surface formed on an inside wall of the pipe fitting. The sealing ring is received in a sealing ring groove defined in the inside wall of the pipe fitting. The pipe fitting has a tube end forming a holding bore having an inside diameter smaller than a diameter of the converging surface. The tube end of the pipe fitting forms openings through which a tool can extend into the pipe fitting to contract the C-clip for releasing the C-clip and the pipe.

Abstract: A releasable nut-free C-clip secured pipe fitting includes a pipe to be jointed, a C-clip, a sealing ring, and a pipe fitting. The pipe has a jointed end forming a circumferential groove for receiving the C-clip. The C-clip is a ring like member having an opening, which allows for expansion and contraction of the C-clip so as to allow the C-clip to be disposed in a converging surface formed on an inside wall of the pipe fitting. The sealing ring is received in a sealing ring groove defined in the inside wall of the pipe fitting. The pipe fitting has a tube end forming a holding bore having an inside diameter smaller than a diameter of the converging surface. The tube end of the pipe fitting forms openings through which a tool can extend into the pipe fitting to contract the C-clip for releasing the C-clip and the pipe.

Abstract: Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.

Abstract: The invention relates to the active lactam compounds with inhibitory effect (anti-proliferative effect) on cancer cells, which are isolated from adlay (Coix lachryma-jobi L. var. ma-yuen Stapf) bran. In the present invention, structures and activities in vitro of the active lactam compounds are further characterized. The active compounds exhibited a strong anti-proliferative effect on cancer cells, such as human lung cancer cell and human colorectal carcinoma cell.

Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

Abstract: The interior of the stop valve is partitioned into an upper chamber where the valve mechanism is installed and a lower chamber where a filter is provided. The two chambers are conducted via a through hole of the partition and are connected to two lateral tubular sockets of the stop valve, respectively. The stop valve can further contain a locking mechanism to securely connect a pipe to the stop valve. The locking mechanism mainly contains a tubular element that can be screwed into a tubular socket and a rubber ring washer at the interface between the pipe and a chamber of the stop valve.

Abstract: To couple a giving end of a first pipe and an receiving end of a second pipe, the device contains a rubber ring, a tubular screw, a C-shaped ring, and a rubber washer. The C-shaped ring is embedded in a groove of the giving end of the first pipe which is threaded through the rubber ring, the tubular screw and the rubber washer and is plugged into the receiving end of second pipe. Inside the tubular screw, the diameter is gradually shrunk to form a born-shaped space with a slant wall. When the tubular screw is screwed into the receiving end of the second pipe, the slant wall forces the C-shaped ring, and thereby the giving end of the first pipe, to gradually advance. In the mean time, the bottom of the tubular screw presses the rubber washer tightly against the second pipe to effectively prevent leakage.

Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

Abstract: A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.

Abstract: A mixed-mode process introduces a hard mask layer. Due to the introduced hard mask layer made of non-resist material formed over devices, performance of a formed capacitor is protected from effects of an implantation process such as source/drain implantation. A self-aligned silicide (salicide) process for a MOSFET transistor can also be performed. Thus, production efficiency and performance of an IC product formed by the mixed-mode process can be improved. Moreover, the number of required fabrication steps is reduced and cost savings can be realized.

Abstract: A mixed-mode process introduces a hard mask layer. Due to the introduced hard mask layer made of non-resist material formed over devices, performance of a formed capacitor is protected from effects of an implantation process such as source/drain implantation. A self-aligned silicide (salicide) process for a MOSFET transistor can also be performed. Thus, production efficiency and performance of an IC product formed by the mixed-mode process can be improved. Moreover, the number of required fabrication steps is reduced and cost savings can be realized.

Abstract: A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.

Abstract: A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.

Abstract: Provided is a process for forming a semiconductor device having salicided contacts. A concentration of metal is formed at the substrate surface by exposing the substrate to a metal plasma. The concentration of metal is then annealed to produce a salicided contact. In a separate embodiment, the metallization plasma and salicide anneal occur in-situ in one process step.

Abstract: A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.

Abstract: The present invention discloses an apparatus and method for cleaning an exhaust conduit that has chemical substances deposited on its inside wall by utilizing a shaft that has a plurality of scraping elements mounted thereto capable of making vertically or radially oscillating motions inside the exhaust conduit such that the chemical substances can be dislodged from the inside wall and the exhaust conduit can be effectively cleaned. The apparatus may optionally include fluid nozzles provided in the shaft for dispensing a cleaning fluid during the cleaning process to further enhance the efficiency. The apparatus may further include a vacuum device for effectively removing the debris dislodged from the inside wall during such cleaning process.

Abstract: A method for blocking formation of a reacted metal layer on a structure in an integrated circuit. The integrated circuit has a source region, a drain region, a gate, an isolation area formed of a material, and a protective layer formed of substantially the same material as the isolation area. The protective layer overlies at least the source region and the drain region. The method is accomplished while reducing an amount of the material of the isolation area that is removed when the material of the protective layer is removed. A blocking layer is deposited on the integrated circuit. The blocking layer is formed of a material that is substantially different from the material of the isolation area and the protective layer. The blocking layer is patterned to selectively cover portions of the blocking layers that overlie at least the structure and selectively expose portions of the blocking layer that overlie at least the source region, the drain region, and the gate.

Abstract: A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer.

Abstract: A method for planarizing an integrated circuit. The integrated circuit is to be planarized to an upper surface using chemical mechanical polishing. The upper surface of the integrated circuit includes regions of a first material and regions of a second material. The first material has a first polishing rate and desired chemical, physical, and electrical properties. The second material has a second polishing rate and desired chemical, physical, and electrical properties. The first polishing rate is greater than the second polishing rate. The regions of the first material adjoin the regions of the second material at interfaces. The upper surface of the integrated circuit is overlaid with a top layer of the second material, that is to be removed by the chemical mechanical polishing. Both the regions of the second material and the top layer of the second material are deposited during a deposition.

Abstract: A wafer mounting plate for mounting a wafer in a chemical mechanical polishing process and a method for using the wafer mounting plate are disclosed. The novel mounting plate for a silicon wafer is designed to incorporate a concave mounting surface for contacting a wafer with a flexible membrane layer thereinbetween. The wafer mounting plate is further provided with a plurality of apertures therethrough for use as vacuum passageways for picking up a wafer through a perforated or breathable membrane layer. The concave surface of the wafer mounting plate that contacts the wafer substantially eliminates stress concentration problems imposed on the wafer by conventional wafer mounting plates. The present invention novel apparatus therefore not only eliminates the edge defect problem that is normally associated with the conventional mounting plates, but further solves the wafer breakage problem frequently caused by stress concentration imposed on the wafer by a bumper ring.