Patents by Inventor Ming Yu

Ming Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240103097
    Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 28, 2024
    Inventors: Xin Zheng, Wenjing Yu, Tao Peng, Yi Fang, Ming Lei, Hong Shi, Ben Ma, Li Ding, Wei Wei, Linghua Li, He Yu, Tian Xia, Yingchun Wang, Sike Wang, Dongri Xie, Xin Wang, Bo Pang, Xianjin Rong
  • Patent number: 11941338
    Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yi Hu, Chih-Ming Chao, Chi-Yeh Yu
  • Patent number: 11943030
    Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The UE includes a plurality of antenna panels. The method includes transmitting, to a Base Station (BS), a UE capability message that includes a number of the plurality of antenna panels; and transmitting, to the BS, a panel report that includes information of the plurality of antenna panels, the information associated with at least one of a Synchronization Signal Block (SSB) and a Channel State Information Reference Signal (CSI-RS).
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 26, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Chia-Hao Yu, Hsin-Hsi Tsai, Chie-Ming Chou
  • Patent number: 11942385
    Abstract: A semiconductor package includes a substrate having a first side and a second side opposite to the first side, a first type semiconductor die disposed on the first side of the substrate, a first compound attached to the first side and encapsulating the first type semiconductor die, and a second compound attached to the second side, causing a stress with respect to the first type semiconductor die in the first compound. A method for manufacturing the semiconductor package described herein is also disclosed.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: March 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Yu Chen, Chang-Lin Yeh, Ming-Hung Chen
  • Patent number: 11943170
    Abstract: A method includes: An access point generates an NDPA frame, where the NDPA frame includes a station information field, and the station information field includes an AID subfield indicating an association identifier AID of a station; the station information field further includes a partial bandwidth information subfield; the partial bandwidth information subfield indicates an RU that is in a bandwidth corresponding to the NDPA frame and for which the station needs to feed back channel state information; and the bandwidth corresponding to the NDPA frame is greater than 160 MHz. The access point transmits the NDPA frame.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: March 26, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jian Yu, Yuchen Guo, Chenchen Liu, Yunbo Li, Ming Gan, Dandan Liang
  • Patent number: 11943052
    Abstract: Embodiments of this application provide data processing methods and apparatuses. One method includes: inputting all bits in a coded bitstream into a first interleaver or a first tone mapper, wherein the coded bitstream is allocated to M resource units (RUs) allocated for a first user, and M is an integer greater than 1, and reordering all bits in the coded bitstream by using the first interleaver or the first tone mapper.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jian Yu, Ming Gan
  • Publication number: 20240098932
    Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.
    Type: Application
    Filed: July 19, 2023
    Publication date: March 21, 2024
    Applicant: Acer Incorporated
    Inventors: Hui-Ping Sun, Jui-Yi Yu, Chun-Hung Wen, Yen-Chou Chueh, Yu-Ming Lin, Chun-Hsien Chen
  • Publication number: 20240093556
    Abstract: A drill bit for cutting formation comprises a bit body, a plurality of cutters, and a plurality of blades with pockets to accommodate the cutters, respectively. Each of the plurality of cutters has a substrate, an ultra-hard layer, an inclined surface on the top of the ultra-hard layer, wherein the inclined surface slants downward from a cutting edge to a trailing edge. The cutter can improve cutting efficiency and service life.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicants: CNPC USA CORPORATION, BEIJING HUAMEI INC., CHINA NATIONAL PETROLEUM CORPORATION
    Inventors: Jiaqing YU, Chris Cheng, Xu Wang, Ming Yi, Chi Ma
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240095989
    Abstract: Apparatuses, systems, and techniques to generate a video using two or more images comprising objects to be included in the video. In at least one embodiment, objects are identified in two or more images using one or more neural networks, to generate a video to include the objects in the video.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Arun Mohanray Mallya, Ting-Chun Wang, Ming-Yu Liu
  • Publication number: 20240097009
    Abstract: A semiconductor structure includes a substrate, a channel region, a gate structure, and source/drain regions. The channel region is over the substrate. The gate structure is over the channel region, and includes a high-k dielectric layer, a tungsten layer over the high-k dielectric layer, and a fluorine-containing work function layer over the tungsten layer. The source/drain regions are at opposite sides of the channel region.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. SAVANT, Tien-Wei YU, Ke-Chih LIU, Chia-Ming TSAI
  • Publication number: 20240091838
    Abstract: A forming method of a processing curve in a stamping process is provided. The method includes the following steps. A plurality of processing curves are established, and an optimization target is set for the processing curves according to material characteristics of a workpiece, process requirements and a finished product CAD file. At least two of the processing curves are selected and superimposed to form a basic forming curve, wherein each subsection of the basic forming curve corresponds to a selected processing curve. Whether the selected processing curve in each subsection of the basic forming curve matches the optimization target is determined.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 21, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Huang SHIEH, Hsuan-Yu HUANG, Ming-Cheng TSAI, Yi-Ping HUANG
  • Publication number: 20240097842
    Abstract: A method includes: A station receives a trigger frame from an access point. The trigger frame is used to trigger the station to perform EHT TB PPDU transmission, the trigger frame further indicates a resource unit allocated to the station, and the trigger frame includes first indication information indicating that the station can perform EHT TB PPDU transmission on a portion of the allocated resource unit. The station sends an EHT TB PPDU based on an indication of the first indication information.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Yuxin LU, Ming GAN, Jian YU, Yunbo LI, Chenchen LIU, Bo GONG
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Publication number: 20240098959
    Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20240098753
    Abstract: A method comprises: a second communication apparatus sends a trigger frame, to trigger at least one first communication apparatus that includes a first communication apparatus to transmit an uplink PPDU. After receiving the trigger frame, the at least one first communication apparatus sends the PPDU to the second communication apparatus based on the trigger frame. The PPDU includes a data field and an STF sequence, the data field is carried in a distributed RU, the distributed RU includes a plurality of subcarrier groups that are discrete in frequency domain, one of the subcarrier groups includes one subcarrier or includes at least two consecutive subcarriers, the STF sequence is carried on all subcarriers of a plurality of consecutive RUs, the plurality of consecutive RUs are consecutive RUs corresponding to the distributed RU, and each of the consecutive RUs includes a plurality of subcarriers that are consecutive in frequency domain.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Bo GONG, Chenchen LIU, Mengshi HU, Jian YU, Ming GAN
  • Patent number: 11932534
    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hua Lin, Chang-Ming Wu, Chung-Yi Yu, Ping-Yin Liu, Jung-Huei Peng
  • Patent number: 11931417
    Abstract: Methods are provided for producing a PEGylated interleukin 11 (IL-11) by treating a recombinant IL-11 PEGylated with an equimolar to low molar excess of PEG carrying an amine-reactive group to achieve a highly pure monoconjugate preparation, which provides improved half-life in serum while having desirable therapeutic activity and presenting fewer side-effects. Most preferably, the IL-11 is an N-terminally truncated human or humanized IL-11 and has a 20 Kd or 40 Kd branched PEG moiety, Y- or comb-shaped in particular, coupled to the N-terminal amino group. Such compounds are characterized by substantially increased stability in serum and sustained biological activity while exhibiting significantly reduced plasma expansion.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: March 19, 2024
    Assignee: Nansha Biologics (Hong Kong) Limited
    Inventors: Kuo-Ming Yu, Qui-Lim Choo, Manson Fok, Johnson Yiu-Nam Lau
  • Patent number: 11934959
    Abstract: Apparatuses, systems, and techniques are presented to synthesize consistent images or video. In at least one embodiment, one or more neural networks are used to generate one or more second images based, at least in part, on one or more point cloud representations of one or more first images.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 19, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Arun Mallya, Ting-Chun Wang, Ming-Yu Liu, Karan Sapra
  • Patent number: 11937266
    Abstract: A method and apparatus are disclosed. In an example from the perspective of a first device, a grant is received from a network node. The grant allocates a set of sidelink data resources. One or more sidelink data transmissions are performed on the set of sidelink data resources. A second feedback information associated with the one or more sidelink data transmissions is received and/or detected. An uplink resource is derived. A first feedback information is transmitted on the uplink resource to the network node. The first feedback information is set based upon the second feedback information.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: March 19, 2024
    Assignee: ASUSTek Computer Inc.
    Inventors: Ming-Che Li, Li-Chih Tseng, Wei-Yu Chen, Li-Te Pan