Patents by Inventor Mingyuan Xu

Mingyuan Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11323129
    Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 3, 2022
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie Pu, Gangyi Hu, Dongbing Fu, Zhengping Zhang, Liang Li, Ting Li, Daiguo Xu, Mingyuan Xu, Xiaofeng Shen, Xianjie Wan, Youhua Wang
  • Publication number: 20220117591
    Abstract: An adsorption head includes a body. The body is a hollow housing, one side of the housing to which an adsorbed object is adsorbed is provided with an opening. The body comprises at least one adsorption chamber and at least one operation chamber therein, wherein the operation chamber and the adsorption chamber are spaced from each other and each have an opening orientated to the adsorbed object. The body has at least one adsorption passage and at least one operation passage thereon, wherein one end of the adsorption passage is communicated with the adsorption chamber, and one end of the operation passage is communicated with the operation chamber.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 21, 2022
    Applicant: DEKE MEDTECH (HANGZHOU) INC.
    Inventors: Nan SHAO, Zhiming WU, Zhenjun ZI, Jingjing HU, Mingyuan XU
  • Publication number: 20220111242
    Abstract: The application provides a yoga tension ring for fitness use, including a tension ring body, the two sides of the yoga tension ring which are in contact with the human body will not curl due to the stretching during the fitness use of stride, buttock bridge, thigh, buttock, up and down squat, lateral movement, etc., and the side of the tension loop body in contact with the human body is detachably provided with an anti-curling device for preventing the curling of the two sides of the tension loop body due to stretching during movement.
    Type: Application
    Filed: May 26, 2021
    Publication date: April 14, 2022
    Inventors: Linlin Li, Mingyuan Xu
  • Patent number: 11290091
    Abstract: The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 29, 2022
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Xi Chen, Xiaofeng Shen, Xingfa Huang, Liang Li, Mingyuan Xu, Jian'an Wang, Dongbing Fu, Guangbing Chen
  • Publication number: 20220091184
    Abstract: The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK?) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK?) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.
    Type: Application
    Filed: January 7, 2020
    Publication date: March 24, 2022
    Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
    Inventors: MINGYUAN XU, LIANG LI, JUN LIU, XIAOFENG SHEN, JIANAN WANG, DONGBING FU, GUANGBING CHEN, XINGFA HUANG, XI CHEN
  • Publication number: 20220052673
    Abstract: The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 17, 2022
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Xi CHEN, Xiaofeng SHEN, Xingfa HUANG, Liang LI, Mingyuan XU, Jian'an WANG, Dongbing FU, Guangbing CHEN
  • Patent number: 11251788
    Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: February 15, 2022
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Xi Chen, Liang Li, Guangbing Chen, Yuxin Wang, Dongbing Fu, Xingfa Huang, Mingyuan Xu, Xiaofeng Shen
  • Publication number: 20210280513
    Abstract: The present disclosure provides a one-time programmable capacitive fuse bit, including an upper plate, the upper plate includes a plurality of fuses arranged side by side and spaced by an internal from each other, middle portions of two adjacent fuses are connected to each other; a connecting portion connected to the fuse is disposed above two ends and the middle portion of each of the plurality of fuses; the fuse bit further includes a lower plate corresponding to the two ends and the middle portion of the fuse, the lower plate is disposed below the fuse; the lower plate corresponding to the middle portion of the fuse is opposite to the connecting portion corresponding to the middle portion of the fuse; a hollow portion is disposed between the lower plate corresponding to the middle portion of the fuse and the lower plate corresponding to both ends of the fuse.
    Type: Application
    Filed: July 18, 2018
    Publication date: September 9, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Mingyuan XU, Shuiqin YAO, Liang Li, Xiaofeng SHEN, Hongrui YANG, Jian'an WANG, Dongbing FU, Guangbing CHEN, Xingfa HUANG, Xi CHEN
  • Publication number: 20210211122
    Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.
    Type: Application
    Filed: July 21, 2017
    Publication date: July 8, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Xi Chen, Liang Li, Guangbing Chen, Yuxin Wang, Dongbing Fu, Xingfa Huang, Mingyuan Xu, Xiaofeng Shen
  • Publication number: 20210184689
    Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 17, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie PU, Gangyi HU, Dongbing FU, Zhengping ZHANG, Liang LI, Ting LI, Daiguo XU, Mingyuan XU, Xiaofeng SHEN, Xianjie WAN, Youhua WANG
  • Publication number: 20210135641
    Abstract: The present disclosure provides a clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.
    Type: Application
    Filed: July 25, 2018
    Publication date: May 6, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Xiaofeng SHEN, Xingfa HUANG, Liang LI, Xi CHEN, Mingyuan XU, Jian'an WANG, Dongbing FU, Guangbing CHEN
  • Patent number: 10389787
    Abstract: Embodiments of the present invention relate to a method, an apparatus and a system for transmitting a media stream. The method is executed by an access terminal, includes: establishing a real-time collaboration channel between the access terminal and a network computer; sending through a first VDI channel to the network computer an operation instruction input by a user; receiving a real-time collaboration message that is sent through the real-time collaboration channel by the network computer; performing, through the network computer, media negotiation with a communication device, so as to determine a media attribute parameter that is used to transmit a media stream between the access terminal and the communication device; and transmitting, by the access terminal, a media stream mutually with the communication device according to the media attribute parameter determined through the media negotiation.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 20, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Mingyuan Xu, Qiang Yan
  • Patent number: 9893931
    Abstract: A connection recovery method includes searching, by a first terminal, for a recovery candidate corresponding to an interrupted connection; selecting, by the first terminal, one found recovery candidate as a first recovery candidate; sending, by the first terminal, a negotiation request to a second terminal; receiving, by the first terminal, a matching success message returned by the second terminal; and transmitting, by the first terminal, data to the second terminal according to the first connection information.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 13, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bin Hu, Xin Chen, Mingyuan Xu, Qiang Yan
  • Publication number: 20160112250
    Abstract: A connection recovery method includes searching, by a first terminal, for a recovery candidate corresponding to an interrupted connection; selecting, by the first terminal, one found recovery candidate as a first recovery candidate; sending, by the first terminal, a negotiation request to a second terminal; receiving, by the first terminal, a matching success message returned by the second terminal; and transmitting, by the first terminal, data to the second terminal according to the first connection information.
    Type: Application
    Filed: December 22, 2015
    Publication date: April 21, 2016
    Inventors: Bin Hu, Xin Chen, Mingyuan Xu, Qiang Yan
  • Patent number: 9128497
    Abstract: The present invention pertains to a voltage reference circuit based on temperature compensation, comprising positive and negative temperature coefficient generating units, temperature compensation circuit, image circuit and voltage divider. In this circuit, Item T is compensated with Item T, and Item T ln(T) is compensated by Item T in (T), which features a well-targeted compensation performance. The circuit outputs a reference voltage with zero temperature coefficient, which is independent to T and T ln (T). The output voltage value could be defined by adjusting the ratio of resistance in voltage divider. The invention provides a voltage reference circuit featuring good compensation, zero temperature coefficient and adjustable output voltage. The invention has a better compensation than the conventional one and a fixed output voltage, and it totally eliminates the temperature coefficient. The invention has wide application in analog IC and digital/analog mixed IC.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 8, 2015
    Assignee: China Electronic Technology Corporation, 24th Research Institute
    Inventors: Ting Li, Zhengfan Zhang, Mingyuan Xu, Yuxin Wang, Tao Liu
  • Publication number: 20150081796
    Abstract: Embodiments of the present invention relate to a method, an apparatus and a system for transmitting a media stream. The method is executed by an access terminal, includes: establishing a real-time collaboration channel between the access terminal and a network computer; sending through a first VDI channel to the network computer an operation instruction input by a user; receiving a real-time collaboration message that is sent through the real-time collaboration channel by the network computer; performing, through the network computer, media negotiation with a communication device, so as to determine a media attribute parameter that is used to transmit a media stream between the access terminal and the communication device; and transmitting, by the access terminal, a media stream mutually with the communication device according to the media attribute parameter determined through the media negotiation.
    Type: Application
    Filed: November 25, 2014
    Publication date: March 19, 2015
    Inventors: Mingyuan XU, Qiang YAN
  • Publication number: 20130328620
    Abstract: The present invention pertains to a voltage reference circuit based on temperature compensation, comprising positive and negative temperature coefficient generating units, temperature compensation circuit, image circuit and voltage divider. In this circuit, Item T is compensated with Item T, and Item T ln(T) is compensated by Item T in (T), which features a well-targeted compensation performance. The circuit outputs a reference voltage with zero temperature coefficient, which is independent to T and T ln (T). The output voltage value could be defined by adjusting the ratio of resistance in voltage divider. The invention provides a voltage reference circuit featuring good compensation, zero temperature coefficient and adjustable output voltage. The invention has a better compensation than the conventional one and a fixed output voltage, and it totally eliminates the temperature coefficient. The invention has wide application in analog IC and digital/analog mixed IC.
    Type: Application
    Filed: August 24, 2011
    Publication date: December 12, 2013
    Inventors: Ting Li, Zhengfan Zhang, Mingyuan Xu, Yuxin Wang, Tao Liu
  • Patent number: 8531323
    Abstract: A pipeline A/D converter and its single redundancy bit digital correction are provided. The single redundancy bit digital correction includes the following steps: substages except for the last one quantizes input voltage, calculates the residual voltage, which is amplified and shifted to the middle part of the reference voltage range, and outputs to the following substage until the last one, which only quantizes the input voltage; the code and offset code of each substage corresponding to the quantized thermometer code are calculated; the offset codes of all stages are added by weight to get total offset code; and codes of all substages are added by weight, to which the total offset code is added. The comparator offset error is corrected to obtain an output code which identifies the negative or positive overflow of input signals. The A/D converter adopting the above digital correction is provided.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: September 10, 2013
    Assignee: No. 24th Research Institute of China Electronics Technology Group Corp
    Inventors: Ting Li, Yuxin Wang, Xiaofeng Shen, Shutao Zhou, Tao Liu, Mingyuan Xu, Ruzhang Li, Kaiquan He
  • Publication number: 20110279295
    Abstract: The present invention pertains to the technical field of A/D converter, to be more specific, a pipeline A/D converter and its single redundancy bit digital correction. The related single redundancy bit digital correction features the following steps: substages except for the last one quantizes input voltage, calculates the residual voltage, which is amplified and shifted to the middle part of the reference voltage range, and outputs to the following substage until the last one, which only quantizes the input voltage; The code and offset code of each substage, corresponding to the quantized thermometer code is calculated; the offset codes of all stages are added by weight to get total offset code; codes of all substages are added by weight, to which the total offset code is added.
    Type: Application
    Filed: June 21, 2010
    Publication date: November 17, 2011
    Applicant: No. 24th Research Institute of China Electronics T echnology Group Corp
    Inventors: Ting Li, Yuxin Wang, Xiaofeng Shen, Shutao Zhou, Tao Liu, Mingyuan Xu, Ruzhang Li, Kaiquan He