Abstract: An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.

Abstract: An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.

Abstract: A sales supporting system is described, a representative one of which includes a sales support system for supporting work of a salesperson of commodities, comprising: input means for entering life information regarding life of a customer; commodity selection support information generating means for generating commodity selection support information for supporting selection by the salesperson of a commodity for health of the customer on the basis of the life information entered by using the input means; and output means for outputting the commodity selection support information generated by the commodity selection support information generating means.

Abstract: A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

Abstract: A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits the distribution request to a program distribution device and transmits the device information to an inspection device. The program distribution device transmits the program in the distribution request to the inspection device. The inspection device inspects a materialization state of the information contents in the terminal device based on the program and the device information and transmits a result of the inspection to the program distribution device and the contents distribution device.

Abstract: A semiconductor integrated circuit including a digital circuit and an analog circuit which are integrated on a single semiconductor chip comprises a first electrostatic destruction protection circuit, connected to a digital circuit, for protecting the digital circuit from destruction caused by ESD therein by an influence of an input digital signal and a second electrostatic destruction protection circuit, connected to an analog circuit, for protecting the analog circuit from destruction caused by ESD therein by an influence of an input analog signal. A first grounding conductor connected to the first electrostatic destruction protection circuit and a second grounding conductor connected to the second electrostatic destruction protection circuit are connected to each other outside the semiconductor integrated circuit.

Abstract: The device will make it easy to recognize an individual object located at a specific location using radio frequency ID tags. The device includes an object having an object main body, a tag provided with the object main body, and a display section provided with the object main body to display the information corresponding to the ID information stored on the tag.

Abstract: A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing invariability for the inputted models, a step of using the models of the applications and the parameters representing invariability as inputted information and comparing the parameters representing invariability to a boundary condition, and a step of allocating one of the application models to programmable logic and another of the application models to an exclusive-use hardware based on a result of the comparison.

Abstract: A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.

Abstract: A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2n bits in length.

Abstract: A semiconductor integrated circuit including a digital circuit and an analog circuit which are integrated on a single semiconductor chip comprises a first electrostatic destruction protection circuit, connected to a digital circuit, for protecting the digital circuit from destruction caused by ESD therein by an influence of an input digital signal and a second electrostatic destruction protection circuit, connected to an analog circuit, for protecting the analog circuit from destruction caused by ESD therein by an influence of an input analog signal. A first grounding conductor connected to the first electrostatic destruction protection circuit and a second grounding conductor connected to the second electrostatic destruction protection circuit are connected to each other outside the semiconductor integrated circuit.

Abstract: In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142, respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142, respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

Abstract: A data classification supporting method capable of easily discriminating a cell to which unknown data belongs and cells similar to the unknown data from each other is obtained. This classification compares cell vector data of each cell with the unknown data, decides a cell having cell vector data closest to the unknown data and cells having cell vector data secondly to nthly close to the unknown data as a minimum cell and similar cells respectively and displays a minimum cell mark and similar cell marks indicating the minimum cell and the similar cells respectively on a classification map.

Abstract: An execution control instruction is applied to an information processor of the type processing instructions by pipelining to suppress the occurrence of branch hazard. The execution control instruction contains: a condition field for specifying an execution condition; and an instruction-specifying field for defining, in binary code, the number of instructions to be executed only conditionally. In response to the execution control instruction, a nullification controller decides, based on control flags provided from an arithmetic logic unit, whether or not the execution condition specified by the condition field is satisfied. And based on the outcome of this decision, the controller determines whether or not that number of instructions, which has been defined by the instruction-specifying field for instructions succeeding the execution control instruction, should be nullified.

Abstract: Adequately assigning features provided by the system to processing units having different architectures incorporated in a system LSI

Abstract: To enable high-speed CRC operation and flexible use of various generating polynomials without causing significant increase in circuit scale, the CRC operation unit uses circuits generally provided for a DSP and some additional circuits.

Abstract: A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions, a decoding unit that decodes the instructions fetched by the instruction fetching unit; and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register-register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data. The first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs new path metrics.

Abstract: An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.

Abstract: In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142, respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142, respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

Abstract: To enable high-speed CRC operation and flexible use of various generating polynomials without causing significant increase in circuit scale, the CRC operation unit uses circuits generally provided for a DSP and some additional circuits. The CRC operation unit includes: a generating polynomial supply section having a first general register for storing an arbitrary generating polynomial and a selector for selectively outputting the generating polynomial or data of which all bits has a value of 0; an operation data supply section having a memory, a shift register, a second general register, and a barrel shifter, for outputting operation data for CRC operation based on transmitting/receiving data; an operation section for performing CRC operation using the generating polynomial output from the generating polynomial supply section and the operation data output from the operation data supply section; and an operation instruction execution control section for controlling the operations of the above sections.