Patents by Inventor Min-woo Song
Min-woo Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862571Abstract: A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.Type: GrantFiled: March 14, 2022Date of Patent: January 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Gug Min, Younhee Kang, Min-Woo Song
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Patent number: 11588039Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.Type: GrantFiled: November 25, 2019Date of Patent: February 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-hyeong Lee, Hoon-joo Na, Sung-in Suh, Min-woo Song, Byoung-hoon Lee, Hu-yong Lee, Sang-jin Hyun
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Publication number: 20220336672Abstract: A semiconductor device includes a substrate, an oxide semiconductor film on the substrate, a first gate structure on the oxide semiconductor film and a contact that is in contact with the oxide semiconductor film, the contact being disposed on a boundary surface with the oxide semiconductor film, and including a metal oxide film that includes a transition metal.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Min Hee CHO, Woo Bin SONG, Hyun Mog PARK, Min Woo SONG
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Patent number: 11417772Abstract: A semiconductor device includes a substrate, an oxide semiconductor film on the substrate, a first gate structure on the oxide semiconductor film and a contact that is in contact with the oxide semiconductor film, the contact being disposed on a boundary surface with the oxide semiconductor film, and including a metal oxide film that includes a transition metal.Type: GrantFiled: January 31, 2020Date of Patent: August 16, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Min Hee Cho, Woo Bin Song, Hyun Mog Park, Min Woo Song
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Publication number: 20220199549Abstract: A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.Type: ApplicationFiled: March 14, 2022Publication date: June 23, 2022Inventors: Byoung-Gug MIN, Younhee KANG, Min-Woo SONG
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Patent number: 11296037Abstract: A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.Type: GrantFiled: October 30, 2019Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Gug Min, Younhee Kang, Min-Woo Song
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Patent number: 11231763Abstract: Various embodiments of the present invention relate to an electronic device and a method for controlling heat generated on the surface of the electronic device. The electronic device may comprise a display and a processor, wherein the processor: displays, on the display, graphic elements at the request of a first application; during a first period of time, acquires first information corresponding to the graphic performance of the displayed graphic elements, and identifies a clock control level for controlling operation performance according to execution of the first application; and during a second period of time following the first period of time, identifies a clock value corresponding to the identified clock control level on the basis of the acquired first information, and controls the operation performance according to execution of the first application by using the identified clock value.Type: GrantFiled: December 6, 2017Date of Patent: January 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Min Lee, Kwang-Eun Go, Kang-Sik Kim, Dong-Sub Kim, Young-San Kim, Won-Min Kim, Young-Hyun Ban, Min-Woo Song, Chung-Hyo Jung
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Patent number: 11177364Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.Type: GrantFiled: July 24, 2020Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Hoon Lee, Hoon-Joo Na, Sung-In Suh, Min-Woo Song, Chan-Hyeong Lee, Hu-Yong Lee, Sang-Jin Hyun
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Publication number: 20210283951Abstract: A wheel hub includes an inner hub part made of a first material and comprising a central portion formed to protrude in an axially inward direction and a flange portion formed to extend in a radially outward direction from the central portion; and an outer hub part made of a second material, which is lower in strength and lighter in weight than the first material, and configured to be integrally coupled with the inner hub part. The flange portion comprises a plurality of main extended portions in which a plurality of fastening holes are formed to penetrate in an axial direction while being arranged to be spaced apart from each other along a circumferential direction so that a wheel is mounted to the flange portion. The plurality of main extended portions are formed to extend along a plurality of virtual extension reference lines which extend in the radially outward direction.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Applicant: ILJIN GLOBAL Co.,LtdInventors: In Ha LEE, Min Woo SONG, Seon Ho LEE, Hee Chan SHIM
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Patent number: 11011473Abstract: Disclosed is a semiconductor package comprising a substrate, a semiconductor chip on the substrate, a molding layer on the substrate covering the semiconductor chip, and a shield layer on the molding layer. The shield layer includes a polymer in which a plurality of conductive structures and a plurality of nano-structures are distributed wherein at least some of the conductive structures are connected to one another.Type: GrantFiled: July 23, 2019Date of Patent: May 18, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Younhee Kang, Byoung-Gug Min, Shi-Kyung Kim, Min-Woo Song, Jae-Seon Hwang
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Publication number: 20210020781Abstract: A semiconductor device includes a substrate, an oxide semiconductor film on the substrate, a first gate structure on the oxide semiconductor film and a contact that is in contact with the oxide semiconductor film, the contact being disposed on a boundary surface with the oxide semiconductor film, and including a metal oxide film that includes a transition metal.Type: ApplicationFiled: January 31, 2020Publication date: January 21, 2021Inventors: Min Hee CHO, Woo Bin SONG, Hyun Mog PARK, Min Woo SONG
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Publication number: 20200365706Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.Type: ApplicationFiled: July 24, 2020Publication date: November 19, 2020Inventors: Byoung-Hoon Lee, HOON-JOO NA, SUNG-IN SUH, MIN-WOO SONG, CHAN-HYEONG LEE, HU-YONG LEE, SANG-JIN HYUN
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Publication number: 20200312783Abstract: A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.Type: ApplicationFiled: October 30, 2019Publication date: October 1, 2020Inventors: Byoung-Gug MIN, Younhee KANG, Min-Woo SONG
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Patent number: 10756195Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.Type: GrantFiled: November 2, 2018Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Hoon Lee, Hoon-Joo Na, Sung-In Suh, Min-Woo Song, Chan-Hyeong Lee, Hu-Yong Lee, Sang-Jin Hyun
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Publication number: 20200194380Abstract: Disclosed is a semiconductor package comprising a substrate, a semiconductor chip on the substrate, a molding layer on the substrate covering the semiconductor chip, and a shield layer on the molding layer. The shield layer includes a polymer in which a plurality of conductive structures and a plurality of nano-structures are distributed wherein at least some of the conductive structures are connected to one another.Type: ApplicationFiled: July 23, 2019Publication date: June 18, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Younhee Kang, Byoung-Gug Min, Shi-Kyung Kim, Min-Woo Song, Jae-Seon Hwang
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Publication number: 20200098882Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Chan-hyeong LEE, Hoon-joo Na, Sung-in Suh, Min-woo Song, Byoung-hoon Lee, Hu-yong Lee, Sang-jin Hyun
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Publication number: 20200073460Abstract: Various embodiments of the present invention relate to an electronic device and a method for controlling heat generated on the surface of the electronic device. The electronic device may comprise a display and a processor, wherein the processor: displays, on the display, graphic elements at the request of a first application; during a first period of time, acquires first information corresponding to the graphic performance of the displayed graphic elements, and identifies a clock control level for controlling operation performance according to execution of the first application; and during a second period of time following the first period of time, identifies a clock value corresponding to the identified clock control level on the basis of the acquired first information, and controls the operation performance according to execution of the first application by using the identified clock value.Type: ApplicationFiled: December 6, 2017Publication date: March 5, 2020Inventors: Jong-Min LEE, Kwang-Eun GO, Kang-Sik KIM, Dong-Sub KIM, Young-San KIM, Won-Min KIM, Young-Hyun BAN, Min-Woo SONG, Chung-Hyo JUNG
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Patent number: 10529816Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.Type: GrantFiled: March 8, 2018Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-hyeong Lee, Hoon-joo Na, Sung-in Suh, Min-woo Song, Byoung-hoon Lee, Hu-yong Lee, Sang-jin Hyun
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Patent number: 10340358Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate, a first active pattern disposed on the substrate and spaced apart from the substrate, a gate insulating film which surrounds the first active pattern, a first work function adjustment film which surrounds the gate insulating film and includes carbon, and a first barrier film which surrounds the first work function adjustment film, in which a carbon concentration of the first work function adjustment film increases as it goes away from the first barrier film.Type: GrantFiled: April 12, 2018Date of Patent: July 2, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung In Suh, Hoon Joo Na, Min Woo Song, Byoung Hoon Lee, Chan Hyeong Lee, Hu Yong Lee, Sang Jin Hyun
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Patent number: 10298045Abstract: A method of controlling an electronic device is provided which includes electrically connecting a battery with an external power source using a first switch such that a first portion of a first current supplied from the external power source is supplied to a system circuit of the electronic device and a second portion of the first current is supplied to the battery, determining whether a specified condition is satisfied, electrically disconnecting the battery from the external power source using the first switch and electrically connecting the battery with a resistor using a second switch, if the specified condition is satisfied, verifying an electrical characteristic of a current applied to the resistor while the battery is electrically disconnected from the external power source and is electrically connected with the resistor, and determining whether an operation of the battery is abnormal, based at least on a part of the electrical characteristic.Type: GrantFiled: July 6, 2017Date of Patent: May 21, 2019Assignee: Samsung Electronics Co., LtdInventors: Hoon Jung, Joo Hoan Do, Min Woo Song, Sung Won Moon, Hyun Seok Lee, Eui Chan Jung, Moo Young Kim, Hyo Seok Na, Ji Woo Lee