Patents by Inventor Miriam Sangalli

Miriam Sangalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210287747
    Abstract: A switching architecture provides input voltage signals from input voltage lines to a plurality of global word lines connected to word lines of a memory array in a memory device. The switching architecture includes a first switching block receiving a first set of positive voltages used to bias unselected word lines and being connected to a first output line providing a first output bias voltage, and a second switching block receiving a second set of positive voltages and a third set of negative voltages used to bias selected word lines and being connected to a second output line providing a second output bias voltage. A plurality of final switches are input connected to the first and second output lines and are output connected to a respective global word line.
    Type: Application
    Filed: March 9, 2021
    Publication date: September 16, 2021
    Applicant: SK hynix Inc.
    Inventors: Marco Passerini, Giulio Maria Iadicicco, Yong Tae KIM, Moon Soo SUNG, Dario Melchionni, Miriam Sangalli
  • Patent number: 7889586
    Abstract: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 15, 2011
    Inventors: Luca Crippa, Giancarlo Ragone, Miriam Sangalli, Rino Micheloni
  • Patent number: 7863967
    Abstract: A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: January 4, 2011
    Inventors: Luca Crippa, Miriam Sangalli, Giancarlo Ragone, Rino Micheloni
  • Patent number: 7777466
    Abstract: A voltage regulator integrated in a chip of semiconductor material is provided.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: August 17, 2010
    Inventors: Luca Crippa, Giancarlo Ragone, Miriam Sangalli, Giovanni Campardo, Rino Micheloni
  • Publication number: 20090262593
    Abstract: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
    Type: Application
    Filed: October 9, 2008
    Publication date: October 22, 2009
    Inventors: Luca Crippa, Giancarlo Ragone, Miriam Sangalli, Rino Micheloni
  • Patent number: 7532061
    Abstract: Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input receiving an enabling signal. A control circuit formed by a plurality of comparators is connected to the high-voltage output and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output and a plurality of reference voltages, one for each comparator. The charge-pump stages are grouped into sets of stages, and the stages belonging to a same set receive a same enabling signal; thus, as many comparators as there are sets of stages are present.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: May 12, 2009
    Inventors: Giancarlo Ragone, Miriam Sangalli, Luca Crippa, Rino Micheloni
  • Patent number: 7521983
    Abstract: A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: April 21, 2009
    Inventors: Giancarlo Ragone, Luca Crippa, Miriam Sangalli, Rino Micheloni
  • Patent number: 7474577
    Abstract: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: January 6, 2009
    Inventors: Luca Crippa, Giancarlo Ragone, Miriam Sangalli, Rino Micheloni
  • Publication number: 20080054864
    Abstract: A voltage regulator integrated in a chip of semiconductor material is provided.
    Type: Application
    Filed: August 24, 2007
    Publication date: March 6, 2008
    Applicant: STMicroelectronics S.R.L.
    Inventors: Luca Crippa, Giancarlo Ragone, Miriam Sangalli, Giovanni Campardo, Rino Micheloni
  • Patent number: 7260005
    Abstract: A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output of the corresponding sense amplifier at least during an evaluating phase of the datum stored in the memory cell. The signal lines include at least two groups of signal lines, arranged such that coupling capacitances between the lines of the first group and the lines of the second group are substantially negligible. The precharging circuit precharges the first group of signal lines to a first voltage level and the second group of signal lines to a second voltage level.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: August 21, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luca Crippa, Miriam Sangalli, Rino Micheloni
  • Publication number: 20070164811
    Abstract: A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.
    Type: Application
    Filed: July 27, 2006
    Publication date: July 19, 2007
    Applicants: STMicroelectronics S.r.I., Hynix Semiconductor Inc.
    Inventors: Luca Crippa, Miriam Sangalli, Giancarlo Ragone, Rino Micheloni
  • Patent number: 7221212
    Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: May 22, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luca Crippa, Miriam Sangalli, Salvatrice Scommegna, Rino Micheloni
  • Publication number: 20070069801
    Abstract: Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input receiving an enabling signal. A control circuit formed by a plurality of comparators is connected to the high-voltage output and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output and a plurality of reference voltages, one for each comparator. The charge-pump stages are grouped into sets of stages, and the stages belonging to a same set receive a same enabling signal; thus, as many comparators as there are sets of stages are present.
    Type: Application
    Filed: May 19, 2006
    Publication date: March 29, 2007
    Applicants: STMicroelectronics S.r.l., Hynix Semiconductor Inc.
    Inventors: Giancarlo Ragone, Miriam Sangalli, Luca Crippa, Rino Micheloni
  • Publication number: 20070053227
    Abstract: A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.
    Type: Application
    Filed: May 19, 2006
    Publication date: March 8, 2007
    Applicants: STMicroelectronics S.r.l., Hynix Semiconductor Inc.
    Inventors: Giancarlo Ragone, Luca Crippa, Miriam Sangalli, Rino Micheloni
  • Publication number: 20060291322
    Abstract: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 28, 2006
    Inventors: Luca Crippa, Giancarlo Ragone, Miriam Sangalli, Rino Micheloni
  • Publication number: 20060164155
    Abstract: The output voltage ripple of a single stage or a multi-stage charge pump may be significantly reduced by introducing in the voltage generator a cascode connected output transistor. In operation, this output transistor may be in a conduction state and may be controlled with a voltage having a smaller ripple than the voltage output by the charge pump.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 27, 2006
    Applicants: STMicroelectronics S.r.l., Hynix Semiconductor Inc.
    Inventors: Giancarlo Ragone, Miriam Sangalli, Rino Micheloni
  • Publication number: 20060140033
    Abstract: A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output of the corresponding sense amplifier at least during an evaluating phase of the datum stored in the memory cell. The signal lines include at least two groups of signal lines, arranged such that coupling capacitances between the lines of the first group and the lines of the second group are substantially negligible. The precharging circuit precharges the first group of signal lines to a first voltage level and the second group of signal lines to a second voltage level.
    Type: Application
    Filed: November 17, 2005
    Publication date: June 29, 2006
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Luca Crippa, Miriam Sangalli, Rino Micheloni
  • Publication number: 20050253644
    Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block.
    Type: Application
    Filed: April 25, 2005
    Publication date: November 17, 2005
    Applicant: STMICROELECTRONICS S.r.I.
    Inventors: Luca Crippa, Miriam Sangalli, Salvatrice Scommegna, Rino Micheloni
  • Patent number: 6493268
    Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: December 10, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Osama Khouri, Andrea Pierin, Rino Micheloni, Stefano Gregori, Guido Torelli, Miriam Sangalli