Patents by Inventor Mirko Dondini

Mirko Dondini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230300001
    Abstract: In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.
    Type: Application
    Filed: February 24, 2023
    Publication date: September 21, 2023
    Inventors: Fred Rennig, Jochen Barthel, Ludek Beran, Mirko Dondini, Vaclav Dvorak, Vincenzo Polisi, Marianna Sanza', CalogeroAndrea Trecarichi, Alfonso Furio
  • Patent number: 11764773
    Abstract: Current absorption management for an electronic fuse coupled between an electrical supply source node and an electrical load node selectively controls a high current electronic switch and a low current electronic switch coupled in parallel between the electrical supply source node and the electrical load node. The high current and low current electronic switches are alternatively actuated: in a first mode where the high current electronic switch is turned on and the low current electronic switch is turned off, and in a second mode where the high current electronic switch is turned off and the low current electronic switch is turned on. Change to the second mode may be made in response to a standby state or a sensing of a lower current in the electrical load. Conversely, change to the first mode may be made in response to a sensing of a higher current in the electrical load.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: September 19, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico Castro, Giovanni Susinna, Vincenzo Randazzo, Mirko Dondini, Calogero Andrea Trecarichi
  • Publication number: 20230187922
    Abstract: Embodiments are directed to electronic fuse devices and systems. One such electronic fuse includes current sensing circuitry that senses a current in a conductor coupled between a power supply and a load, and generates a current sensing signal indicative of the sensed current. I2t circuitry receives the current sensing signal and determines whether the sensed current exceeds an I2t curve of the conductor. The electronic fuse further includes at least one of external MOSFET temperature sensing circuitry that senses a temperature of an external MOSFET coupled to the conductor, low current bypass circuitry that supplies a reduced current to the load in a low power consumption mode during which the external MOSFET is in a non-conductive state, or desaturation sensing circuitry that senses a drain-source voltage of the external MOSFET.
    Type: Application
    Filed: December 12, 2022
    Publication date: June 15, 2023
    Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Vincenzo RANDAZZO, Alberto MARZO, Giovanni SUSINNA, Vanni POLETTO, Antoine PAVLIN, CalogeroAndrea TRECARICHI, Mirko DONDINI, Roberto CRISAFULLI, Enrico CASTRO, Romeo LETOR
  • Patent number: 11644504
    Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: May 9, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mirko Dondini, Daniele Mangano, Salvatore Pisasale
  • Patent number: 11543842
    Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 3, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Mirko Dondini, Daniele Mangano, Riccardo Condorelli
  • Publication number: 20220190816
    Abstract: Current absorption management for an electronic fuse coupled between an electrical supply source node and an electrical load node selectively controls a high current electronic switch and a low current electronic switch coupled in parallel between the electrical supply source node and the electrical load node. The high current and low current electronic switches are alternatively actuated: in a first mode where the high current electronic switch is turned on and the low current electronic switch is turned off, and in a second mode where the high current electronic switch is turned off and the low current electronic switch is turned on. Change to the second mode may be made in response to a standby state or a sensing of a lower current in the electrical load. Conversely, change to the first mode may be made in response to a sensing of a higher current in the electrical load.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 16, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Enrico CASTRO, Giovanni SUSINNA, Vincenzo RANDAZZO, Mirko DONDINI, Calogero Andrea TRECARICHI
  • Publication number: 20220065923
    Abstract: An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.
    Type: Application
    Filed: August 19, 2021
    Publication date: March 3, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mirko DONDINI, Roberto CRISAFULLI, Calogero Andrea TRECARICHI, Vincenzo RANDAZZO
  • Patent number: 11144678
    Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 12, 2021
    Inventors: Mirko Dondini, Gaetano Di Stefano, Sergio Abenda, Layachi Daineche
  • Patent number: 10891399
    Abstract: A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics S.R.L.
    Inventors: Mirko Dondini, Gaetano Di Stefano, Sergio Abenda
  • Patent number: 10788870
    Abstract: A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 29, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Gaetano Di Stefano, Mirko Dondini
  • Publication number: 20200278393
    Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.
    Type: Application
    Filed: February 14, 2020
    Publication date: September 3, 2020
    Inventors: Mirko Dondini, Daniele Mangano, Salvatore Pisasale
  • Publication number: 20200278711
    Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 3, 2020
    Inventors: Mirko DONDINI, Daniele MANGANO, Riccardo CONDORELLI
  • Patent number: 10616333
    Abstract: A system to manage out-of-order traffic in an interconnect network has initiators that provide requests through the interconnect network to memory resource targets and provide responses back through the interconnect network. The system includes components upstream the interconnect network to perform response re-ordering, which include memory to store responses from the interconnect network and a memory map controller to store the responses on a set of logical circular buffers. Each logical circular buffer corresponds to an initiator. The memory map controller computes an offset address for each buffer and stores an offset address of a given request received on a request path. The controller computes an absolute write memory address where responses are written in the memory, the response corresponding to the given request based on the given request offset address.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: April 7, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mirko Dondini, Daniele Mangano
  • Patent number: 10579561
    Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. When the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, when the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 3, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Mirko Dondini, Salvatore Pisasale
  • Publication number: 20190354152
    Abstract: A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 21, 2019
    Inventors: Daniele Mangano, Gaetano Di Stefano, Mirko Dondini
  • Publication number: 20180341791
    Abstract: A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.
    Type: Application
    Filed: April 4, 2018
    Publication date: November 29, 2018
    Inventors: Mirko Dondini, Gaetano Di Stefano, Sergio Abenda
  • Publication number: 20180260585
    Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 13, 2018
    Inventors: Mirko DONDINI, Gaetano DI STEFANO, Sergio ABENDA, Layachi DAINECHE
  • Publication number: 20180217952
    Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. When the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, when the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
    Type: Application
    Filed: March 29, 2018
    Publication date: August 2, 2018
    Inventors: Daniele MANGANO, Mirko DONDINI, Salvatore PISASALE
  • Patent number: 9959226
    Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: May 1, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Mirko Dondini, Salvatore Pisasale
  • Patent number: 9471521
    Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 18, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mirko Dondini, Daniele Mangano, Giuseppe Falconeri