Abstract: An exemplary embodiment provides an efficient solution for protecting electronic systems from counterfeiting and reverse-engineering. The exemplary embodiment may determine the operation of an electronic system by control logic. The control logic may be implemented by finite state machines (FSMs). The exemplary embodiment makes the behavior of the FSMs partially reconfigurable and hiding the configuration data in a secure memory device. With the configuration data stored in a secure memory device, the exemplary embodiment obfuscates the behavior of the FSMs both from the standpoint of the foundry as well as from adversaries.

Abstract: Methods and apparatuses are described herein for securing a mission logic system using one or more distributed, independent programmable security logic blocks. The security logic blocks may monitor subsystems of the mission logic system and/or communication between subsystems. If the security logic blocks determine that the mission logic system is operating in an unauthorized manner, the security logic blocks may enforce a protection mechanism. The security logic blocks may include an interface for receiving communications from the subsystems, an analysis instrument for analyzing the communications, a transport instrument for routing communications from the interface to the analysis instrument, and a control instrument for enforcing the protection mechanism on the basis on an analysis performed by the analysis instrument.

Abstract: Signals sent from one system-on-chip core become switched to a reconfigurable logic core (RLC) for observation and, perhaps, replacement with another signal. A first signal line couples together a plurality of cores. A switch, disposed between the first signal line and an input signal line of the RLC, selectively controls whether the signal gets sent to the RLC. A multiplexer, having the first signal line and an output signal line of the RLC as inputs, selectively controls whether the signal or a replacement signal becomes conveyed to another core of the system-on-chip. Observation and control configuration memory bits act as inputs in the selective control of the switch and the multiplexer. Other embodiments teach shared RLC input signal lines amongst multiple cores. The RLC may contain an inverter, a test circuit, a logic analyzer or other. Methods of observing and replacing signals are also taught.

Abstract: A method that enables testing any point (target point) within a core, including a point within a combinatorial circuit of a core, permits testing of points that are not otherwise unobservable in normal debugging processes. Such a target point is tested by identifying a fanout cone from that point to observable outputs, and by performing one or more tests, where each test sensitizes one or more paths that extend the signal of the target point, or its complement, to one or more of the observable outputs, and ascertains the values at those observable outputs. By having more than one observable output at which the signal of target point (or its complement) is tested significantly increases the level of confidence in the test when the observable points concur in the signal value of the target point.

Abstract: Systems and methods for delay-fault testing field programmable gate arrays (FPGA's), applicable both for off-line manufacturing and system-level testing, as well as for on-line testing within the framework of the roving self-test area (STARs) approach are described. In one described method, two or more paths under test receive a test pattern approximately simultaneously. The two paths are substantially identical and thus should propagate the signal in approximately the same amount of time. An output response analyzer receives the signal from each of the paths and determines the interval between them, and then determines whether a delay fault has occurred based at least in part on the interval. The output response analyzer may include an oscillator and a counter. The oscillator generates an oscillating signal during the interval between when the test signal propagates through the first path and the last path under test.

Abstract: A carbon black monolith comprising a matrix comprising ceramic material and carbon black dispersed throughout the matrix and a method for making a carbon black monolith comprising extruding an extrudable mixture including a carbon black, a ceramic forming material, water, an extrusion aid, and a flux material. A carbon black monolith catalyst comprising a finished self-supporting carbon black monolith having at least one passage therethrough, and comprising a supporting matrix and carbon black dispersed throughout the supporting matrix and at least one catalyst precursor on the finished self-supporting carbon black monolith. A method for making and a method for use of such a carbon black monolith catalyst in catalytic chemical reactions are also disclosed.

Abstract: Serial assertion checking is realized in a System On a Chip (SoC) device by connecting scan chain output to a bit extractor configured within a functionally reconfigurable module that is part of the SoC, which extracts the bits necessary for the assertion checking. The extracted bits are applied to a finite state machine that implements the assertion checking.

Abstract: When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k?1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.

Abstract: When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k?1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.

Abstract: An arrangement that includes a core with a flaw is effectively made error free with an auxiliary circuit that interacts with input and output leads of the core, which detected occurrence of an input that causes an erroneous output at the core, and modified that output either essentially directly, or through changes in accessible core inputs.

Abstract: An SoCs with functionally reconfigurable modules employing the modules to configure circuitry for performing assertion checking. Both at-speed assertion checking as well as continuous single step (CSS) assertion checking is disclosed. Advantageously, the checking of the various cores within the SoC is carried out concurrently, in subsets of the entire set of assertions that need to be checked out. Advantageously, bit extraction and injection is used in CSS assertion checking to permit use of relatively small registers for the assertion checking of each subset of assertions.

Abstract: An autonomous on-chip power management system for managing power consumption of an functional block in an integrated circuit includes power management circuitry configured to monitor signals relevant to the function of the functional block for detecting a predetermined condition associated with the signals, and, in response to the detection of the predetermined condition, to set the functional block to a power saving mode, and, in response to the detection of a predetermined reactivating condition associated with the signals, to set the functional block to a normal operational mode.

Abstract: An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.

Abstract: Techniques for testing a sequential circuit comprising a plurality of flip-flops or other types of registers. The circuit is first configured such that substantially all feedback loops associated with the registers, other than one or more self-loops each associated with a corresponding one of the registers, are broken. Test patterns are then generated for application to the circuit. The test patterns are applied to the circuit in conjunction with partitioned clock signals each of which is associated with a corresponding level of the circuit containing at least one of the self-loops.

Abstract: An SoCs with functionally reconfigurable modules employing the modules to configure circuitry for performing assertion checking. Both at-speed assertion checking as well as continuous single step (CSS) assertion checking is disclosed. Advantageously, the checking of the various cores within the SoC is carried out concurrently, in subsets of the entire set of assertions that need to be checked out. Advantageously, bit extraction and injection is used in CSS assertion checking to permit use of relatively small registers for the assertion checking of each subset of assertions.

Abstract: A method of fault tolerant operation of field programmable gate arrays (FPGAs), whether as an embedded portion of a system-on-chip or other application specific integrated circuit, utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into a self-testing area and a working area. Within the self-testing area, programmable interconnect resources of the FPGA are tested for faults. Upon the detection of one or more faults within the interconnect resources, the faulty interconnect resources are identified and a determination is made whether utilization of the faulty interconnect resources is compatible with an intended operation of the FPGAs. If the faulty interconnect resources are compatible with the intended operation of the FPGA, utilization of the faulty interconnect resource is allowed to provide fault tolerant operation of the FPGA.

Abstract: A method of identifying faulty programmable interconnect resources of a field programmable gate array (FPGA) may be carried out during manufacturing testing and/or during normal on-line operation. The FPGA resources are configured into a working area and a self-testing area. The working area maintains normal operation of the FPGA throughout on-line testing. Within the self-testing area, programmable interconnect resources of the FPGA are grouped and comparatively tested for faults. Upon the detection of one or more faults within a group of programmable interconnect resources, the group of resources is subdivided for further comparative testing in order to minimize a region of the group of resources including the fault for each fault. Once the region of the group of resources which includes the fault is minimized, the wires within the minimized region are comparatively tested in order to determine which wire includes the faulty resource or resources.

Abstract: Systems and methods for delay-fault testing field programmable gate arrays (FPGA's), applicable both for off-line manufacturing and system-level testing, as well as for on-line testing within the framework of the roving self-test area (STARs) approach are described. In one method according to the present invention, two or more paths under test receive a test pattern approximately simultaneously. The two paths are substantially identical and thus should propagate the signal in approximately the same amount of time. An output response analyzer receives the signal from each of the paths and determines the interval between them. The output response analyzer next determines whether a delay fault has occurred based at least in part on the interval. In one embodiment, the output response analyzer comprises an oscillator and a counter.

Abstract: A method of fault tolerant operation of an adaptive computing system includes identifying a faulty resource in a signal path of the adaptive computing system, reconfiguring the signal path to avoid the faulty resource, estimating a time delay created by reconfiguring the signal path, and adjusting a system clock period to accommodate the time delay. In a preferred embodiment, an FPGA is configured into an initial self-testing area and a working area. Resources located within the self-testing area are tested and faulty resources identified. The FPGA is then reconfigured to avoid the identified faulty resources. When the resources are reconfigured for fault tolerant operation, signal path delays may be introduced into the system. If the signal path delays are in a critical path, a period of a system clock may be adjusted in order to insure proper fault tolerant operation.

Abstract: An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.