Patents by Inventor Mirzafer K. Abatchev

Mirzafer K. Abatchev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200203171
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 10607844
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 10600648
    Abstract: A method for processing a stack with a carbon based patterned mask is provided. The stack is placed in an etch chamber. A silicon oxide layer is deposited by atomic layer deposition over the carbon based patterned mask by providing a plurality of cycles, wherein each of the cycles of the plurality of cycles, comprises providing a silicon precursor deposition phase, comprising flowing an atomic layer deposition precursor gas into the etch chamber, where the atomic layer deposition precursor gas is deposited while plasmaless and stopping the flow of the atomic layer deposition precursor gas and providing an oxygen deposition phase, comprising flowing ozone gas into the etch chamber, wherein the ozone gas binds with the deposited precursor gas while plasmaless and stopping the flow of ozone gas into the etch chamber. Part of the silicon oxide layer is etched. The stack is removed from the etch chamber.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 24, 2020
    Assignee: Lam Research Corporation
    Inventors: Tom A. Kamp, Mirzafer K. Abatchev
  • Patent number: 10181412
    Abstract: Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: January 15, 2019
    Assignee: Lam Research Corporation
    Inventors: Alexei Marakhtanov, Mirzafer K. Abatchev, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
  • Publication number: 20180308693
    Abstract: A method for processing a stack with a carbon based patterned mask is provided. The stack is placed in an etch chamber. A silicon oxide layer is deposited by atomic layer deposition over the carbon based patterned mask by providing a plurality of cycles, wherein each of the cycles of the plurality of cycles, comprises providing a silicon precursor deposition phase, comprising flowing an atomic layer deposition precursor gas into the etch chamber, where the atomic layer deposition precursor gas is deposited while plasmaless and stopping the flow of the atomic layer deposition precursor gas and providing an oxygen deposition phase, comprising flowing ozone gas into the etch chamber, wherein the ozone gas binds with the deposited precursor gas while plasmaless and stopping the flow of ozone gas into the etch chamber. Part of the silicon oxide layer is etched. The stack is removed from the etch chamber.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 25, 2018
    Inventors: Tom A. KAMP, Mirzafer K. ABATCHEV
  • Patent number: 10096483
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20180286693
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: May 30, 2018
    Publication date: October 4, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20170372913
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 28, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 9761457
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 12, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 9478497
    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: October 25, 2016
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Mirzafer K. Abatchev
  • Publication number: 20160203993
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 9305782
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greely, Brian J. Coppa
  • Publication number: 20150357209
    Abstract: Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 10, 2015
    Inventors: Alexei Marakhtanov, Mirzafer K. Abatchev, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
  • Patent number: 9117767
    Abstract: Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: August 25, 2015
    Assignee: Lam Research Corporation
    Inventors: Alexei Marakhatanov, Mirzafer K. Abatchev, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
  • Publication number: 20150054168
    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Inventors: David H. Wells, Mirzafer K. Abatchev
  • Publication number: 20150021744
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greely, Brian J. Coppa
  • Patent number: 8895232
    Abstract: The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. A pattern of mandrels is formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized and grown to a desired width. The spacers can then be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, allowing the deposition of more conformal blanket layers and widening the process window for spacer formation.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer K. Abatchev, Gurtej Sandhu
  • Patent number: 8883644
    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Mirzafer K. Abatchev
  • Patent number: 8852851
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph N. Greeley, Brian J. Coppa
  • Publication number: 20140038416
    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
    Type: Application
    Filed: October 14, 2013
    Publication date: February 6, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David H. Wells, Mirzafer K. Abatchev