Abstract: A memory control apparatus is interposed between a central processing unit and a memory device to store data includes a plurality of cache memories to temporarily store data which is transferred between the central processing unit and the memory device and a cache memory control unit having a selector for selecting a cache memory to store data which is transferred from the memory device. The memory control apparatus assigns cache memories to store clean data and dirty data, which is updated data corresponding to the clean data, in accordance with a data identifier, whether a slot number is odd or even, or a usable amount of memory in the cache memories. The memory control apparatus selects a cache memory to store the data so as to almost equalize usage in the plurality of cache memories, thereby controlling the allocation of the cache memories.

Abstract: A memory control apparatus is interposed between a central processing unit and a memory device to store data includes a plurality of cache memories to temporarily store data which is transferred between the central processing unit and the memory device and a cache memory control unit having a selector for selecting a cache memory to store data which is transferred from the memory device. The memory control apparatus assigns cache memories to store clean data and dirty data, which is updated data corresponding to the clean data, in accordance with a data identifier, whether a slot number is odd or even, or a usable amount of memory in the cache memories. The memory control apparatus selects a cache memory to store the data so as to almost equalized usage in the plurality of cache memories, thereby controlling the allocation of the cache memories.

Abstract: A memory control apparatus according to the invention is interposed between a central processing unit and a memory device to store data and has: a channel control unit to control a data transfer to/from the central processing unit; a drive control unit to control a data transfer to/from the memory device; a plurality of cache memories to temporarily store the data which is transferred between the central processing unit and the memory device; and a cache memory control unit having selecting means for selecting the cache memory to store the data which is transferred from the memory device. The memory control apparatus selects the cache memory to store the data so as to almost equalize use amounts in the plurality of cache memories, thereby controlling the allocation of the cache memories and enabling a cache memory space to be effectively used.

Abstract: A memory control apparatus according to the invention is interposed between a central processing unit and a memory device to store data and has: a channel control unit to control a data transfer to/from the central processing unit; a drive control unit to control a data transfer to/from the memory device; a plurality of cache memories to temporarily store the data which is transferred between the central processing unit and the memory device; and a cache memory control unit having selecting means for selecting the cache memory to store the data which is transferred from the memory device. The memory control apparatus selects the cache memory to store the data so as to almost equalize use amounts in the plurality of cache memories, thereby controlling the allocation of the cache memories and enabling a cache memory space to be effectively used.

Abstract: A memory control apparatus interposed between a central processing unit and a memory device to store data includes a channel control unit to control a data transfer to/from the central processing unit; a drive control unit to control a data transfer to/from the memory device; a plurality of cache memories to temporarily store data which is transferred between the central processing unit and the memory device; and a cache memory control unit having a selector for selecting a cache memory to store data which is transferred from the memory device. The memory control apparatus selects a cache memory to which data is to be stored so as to almost equalize usage of the plurality of cache memories, thereby controlling allocation of the cache memories and enabling a cache memory space to be effectively used.