Patents by Inventor Misao Miyata

Misao Miyata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5821786
    Abstract: A semiconductor integrated circuit, having circuit blocks to be evaluated in AC performance, includes a first circuit for inputting a first signal and a second signal generated in the interior of the semiconductor integrated circuit. The first circuit outputs a transient current when the first signal and the second signal change simultaneously. In the semiconductor integrated circuit, the transient current (third signal) is output to a external terminal of the semiconductor integrated circuit for evaluating the AC performance of the block.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: October 13, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Nozuyama, Misao Miyata
  • Patent number: 5155817
    Abstract: A microprocessor employs pipelined architecture and comprises a first execution processor for executing and processing a first kind of instructions among decoded instructions according to microprogram control, a second execution processor for executing and processing a second kind of instructions which are different from the first kind of instructions according to hardwired control, and a controller. The controller issues decoded instructions in a program sequence, selectively determines for each of the decoded instructions which of the first and second execution processors shall execute and process an instruction, and operates the first and second execution processors independently of each other and in parallel with each other.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: October 13, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidechika Kishigami, Misao Miyata
  • Patent number: 4631686
    Abstract: A programmable semiconductor integrated circuit device is disclosed, which includes different kinds of MSI scale function blocks formed on a substrate. First wiring lines extending in a row direction are connected to input terminals of the function blocks, respectively. Second wiring lines are connected to output terminals of the function blocks, respectively. The second wirings are T-shaped and have respective line components extending in a column direction, with the first wiring lines. Floating gate type field effect transistors are provided, in a matrix manner, at mutually electrically insulated crossing points among the first and second lines.
    Type: Grant
    Filed: August 31, 1984
    Date of Patent: December 23, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ikawa, Tadashi Shibata, Kiyoshi Urui, Misao Miyata, Masahiko Kawamura, Noboru Amano