Abstract: Method and apparatus for a computer system to efficiently operate with multiple instruction processors and input/output subsystem in a symmetrical multi-processing environment. The computer system uses a new storage controller having a high performance interconnect scheme that scales in system performance as additional common storage controller modules are added. The interconnect scheme has the cost advantage of a bus connected system while achieving the performance characteristics of a crossbar connected system.

Abstract: Method and apparatus for maximizing cache memory throughput in a system where a plurality of requesters may contend for access to a same memory simultaneously. The memory utilizes an interleaved addressing scheme wherein each memory segment is associated with a separate queuing structure and the memory is mapped noncontiguously within the same segment so that all segments are accessed equally. Throughput is maximized as the plurality of requesters are queued evenly throughout the system.

Abstract: A cache architecture for a multiprocessor data processing system. The cache architecture includes multiple first-level caches, two second-level caches, and main storage that is addressable by each of the processors. Each first-level cache is dedicated to a respective one of the processors. Each of the second-level caches is coupled to the other second-level cache, coupled to the main storage, and coupled to predetermined ones of the first-level caches. The range of cacheable addresses for both of the second-level caches encompasses the entire address space of the main storage. Each of the second-level caches may be viewed as dedicated for write access to the set of processors associated with the predetermined set of first-level caches, and shared for read access to the other set of processors. The dedicated and shared nature enhances system efficiency. The cache architecture includes coherency control that filters invalidation traffic between the second-level caches.

Abstract: Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once deactivated, no further reading or writing is performed at that address location for a predetermined time period. The parity error reporting and address deactivation is accomplished without an access time penalty and requires a reduced number of I/O pins.

Abstract: Method and apparatus for reducing address/function transfer pins in a system where cache memories in a system controller are accessed by a number of instruction processors. The reduction of pins is obtained by using two data transfers. The increase in data addressing time, which would otherwise occur using two data transfers, is reduced to nearly the time of the data transfers themselves by responding to the first data transfer while the second data transfer is taking place.

Abstract: An improved memory request storage and allocation system using parallel queues to retain different categories of memory requests until they can be acted on by the main memory. Memory requests in the parallel queues are allowed to access the main memory according to a queue priority scheme. The queue priority scheme is based on an adjustable ratio, which determines the rate at which memory requests from one queue are allowed to access the main memory versus memory requests from other queues. Registers for bypassing the adjustable ratio eliminate delays by prohibiting the queue priority circuitry from attempting to retrieve a non-existent memory request from a queue. Conflict detection circuitry maintains proper instruction order in the parallel queue architecture by ensuring that subsequent memory requests, which have the same address as a memory request already in the queue, are placed in the same queue in the order that they were entered into the queue.

Abstract: An apparatus and method for transferring data sets between a storage controller and a number of daisy chained main memories on separate circuit elements at high speed. Each main memory has coupled control logic which receives a data set from the storage controller, latches and retransmits the data set to the next main control logic and coupled memory, which next control logic repeats the process, and which can be continued through a number of coupled control logic units and main memories. A data set includes a header with an address range and function information. If data is to be sent from the storage controller it is appended to the header. Each storage controller compares the address range with the address range of the coupled memory, and if within the address range and for a write, will store the appended data in the header address in the coupled memory.

Abstract: A storage lock apparatus for a multiprocessor data processing system. The storage lock apparatus includes control for granting locks to different selectable portions of storage in parallel. In addition, acknowledgment from a remote lock controller is not required for a processor to obtain a lock on an address, even if the address for which the lock was requested is not local relative to the processor. Parallel priority queues are employed for parallel handling of storage lock functions and general storage operations, thereby reducing contention for priority between storage lock operations and general storage operations where there are no addressing conflicts.

Abstract: A dynamic power consumption reduction apparatus for reducing power consumption by temporarily delaying multiple data transfer interfaces. Data transfer interfaces are only delayed in rare circumstances where an exceptionally high number of data transfers are occurring for a period of time. The number of active data transfer interfaces is monitored, and a count value is incremented or decremented depending on the number of active data transfer interfaces. If the count value reaches a threshold value, it indicates that the number of data transfers for a predetermined period of time is exceptionally high, and therefore power consumption is high. Where the number of data transfers is high for a predetermined period of time, delays are injected into the handshake cycle to delay return of data acknowledge signals from data receivers to data transmitters. The delays are discontinued when the data transfer interface activity is reduced to a normal level.

Abstract: An apparatus for and method of efficiently providing a modular dayclock within a data processing system. This is accomplished by dividing the dayclock hardware into a number of dayclock modules configured to operate in a bit serial fashion. This allows the dayclock to accommodate a variety of dayclock word widths by simply varying the number of dayclock modules provided. Further, since the dayclock may operate serially, rather than in parallel fashion, the number of dayclock module I/O's and board route channels may be substantially reduced. Finally, all control logic may be provided directly in the dayclock modules, thereby eliminating the need for a central dayclock controller.

Abstract: A method and apparatus for identifying obsolete data within cache memory in a multiprocessor architecture. This is accomplished while still providing the advantages of having cache resources dedicated to individual instruction processors as well as shared intermediate level cache modules. The technique provides the band pass and attendant performance advantages of an essentially point-to-point architecture without all of the added hardware of a centralized master system storage controller. Further, unlike a strictly point-to-point architecture, the present invention is readily expandable to service a large number of multiprocessors without burdening each of the multiprocessors with the corresponding increase in interface and connection costs of a strictly point-to-point architecture. This simplifies the design of the multiprocessor elements and also allows a system to be expanded to include more or less multiprocessors by simply including a modified XBAR interface.

Abstract: A control method and apparatus for dual slope analog to digital signal conversion is disclosed in which the time required for input signal integration is sensed. A switch connected across the integrator is closed in response to sensing of an integration time which exceeds the integration interval corresponding to a limit of the expected range of input signal values.