Patents by Inventor Mitsuharu Shimizu
Mitsuharu Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030107131Abstract: A semiconductor device includes a semiconductor element having an electrode formation surface on which an electrode terminal and a re-wiring portion are formed. The re-wiring portion is electrically connected to the electrode terminal. An external terminal made of wire has a base end connected to the re-wiring portion and a distal end extending therefrom. An electrically insulating resin covers the electrode formation surface in such a manner that at least the distal end of the external terminal is exposed outside the insulating resin. During a fabricating process, the electrode formation surface is coated with an electrically insulating resin and then a part of the electrically insulating resin is removed from the distal end of the external connecting terminal to expose the same outside the insulating resin.Type: ApplicationFiled: October 29, 1999Publication date: June 12, 2003Applicant: Shinko Electric Industries Co. LtdInventors: MITSUTOSHI HIGASHI, HIDEAKI SAKAGUCHI, KAZUNARI IMAI, MASAHIRO KYOZUKA, MITSUHARU SHIMIZU
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Publication number: 20010028108Abstract: A semiconductor device includes a semiconductor element having an electrode formation surface on which an electrode terminal and a re-wiring portion are formed. The re-wiring portion is electrically connected to the electrode terminal. An external terminal made of wire has a base end connected to the re-wiring portion and a distal end extending therefrom. An electrically insulating resin covers the electrode formation surface in such a manner that at least the distal end of the external terminal is exposed outside the insulating resin. During a fabricating process, the electrode formation surface is coated with an electrically insulating resin and then a part of the electrically insulating resin is removed from the distal end of the external connecting terminal to expose the same outside the insulating resin.Type: ApplicationFiled: June 6, 2001Publication date: October 11, 2001Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Mitsutoshi Higashi, Hideaki Sakaguchi, Kazunari Imai, Masahiro Kyozuka, Mitsuharu Shimizu
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Patent number: 6074567Abstract: A semiconductor package includes a laminate of substrates having a cavity 16, through-holes 25 and circuit patterns, wherein the through-holes 45 and some of the circuit patterns 18 are coated with a plated nickel/gold coating 50.Type: GrantFiled: February 9, 1998Date of Patent: June 13, 2000Assignee: Shinko Electric Industries Co., Ltd.Inventors: Fumio Kuraishi, Toshihisa Yoda, Mitsuharu Shimizu
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Patent number: 5854094Abstract: A process for manufacturing a metal plane support for making multi-layer lead frames adapted to be used for semiconductor devices. The lead frame support is made of a single thin metal strip having a plurality of lead frames continuously arranged in the longitudinal direction, the metal plane support is also made of a single thin metal strip and includes a plurality of metal planes, such as power supply planes, ground planes of the like, continuously arranged in the longitudinal direction corresponding to said plurality of lead frames. A pair of side rails are extending in the longitudinal direction for supporting the metal planes therebetween. The metal planes are connected to the rails via separating portions for removing the rails from the metal planes, after the metal planes are adhered to the corresponding lead frames.Type: GrantFiled: October 1, 1996Date of Patent: December 29, 1998Assignees: Shinko Electric Industries Co., Ltd., Intel CorporationInventors: Hirofumi Fujii, Yoshiki Takeda, Mitsuharu Shimizu
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Patent number: 5804422Abstract: A semiconductor package is produced by the following steps. A plurality of circuit boards are prepared, each board having an opening for forming a cavity and a surface providing with a circuit pattern having bonding sections at a peripheral area of the opening. The bonding sections of the respective circuit boards are covered with protective films. A laminated body is formed by laminating the plurality of circuit boards by means of adhesive sheets arranged between the respective circuit boards. Upper and lower substrates are also laminated on upper and lower surfaces of the plurality of circuit boards, respectively, by means of adhesive sheets to close the cavity. The protective films are subsequently removed from the bonding sections of the respective circuit boards of the laminated body.Type: GrantFiled: September 13, 1996Date of Patent: September 8, 1998Assignee: Shinko Electric Industries Co., Ltd.Inventors: Mitsuharu Shimizu, Toshihisa Yoda
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Patent number: 5576577Abstract: A multi-layer lead-frame for a semiconductor device includes a signal layer made of a metal strip having a signal pattern including a plurality of lead lines. A power supply layer is adhered and laminated to the signal layer and a ground layer is adhered and laminated to the power supply layer. A ceramic plate made of a ferroelectric substance is disposed between the power supply and ground layers. Conductive adhesive material is disposed between said ceramic plate and said first metal layer, and between and adhering to said ceramic plate and said second metal layer.Type: GrantFiled: May 4, 1995Date of Patent: November 19, 1996Assignee: Shinko Electric Industries Co., Ltd.Inventors: Toshikazu Takenouchi, Kuniyuki Hori, Mitsuharu Shimizu
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Patent number: 5410180Abstract: A metal plane support structure of a semiconductor device multi-layer lead frame having one or more metal planes, of different types, arranged in stacked and aligned relationship with and adhered to a corresponding lead frame. Metal planes of a common type are defined in a corresponding metal strip, at longitudinally spaced positions, the metal strip having a pair of side rails along the longitudinal edges thereof, integral support bars extending transversely of the side rails and interconnecting the metal planes to the side rails and section bars extending between and integrally interconnecting the side rails, each section bar disposed between two adjacent metal planes. Separating portions are formed in aligned relationship in the support bars and section bars. The lead frames are defined, further, at longitudinally spaced positions corresponding to the spacing of the metal planes, in a further metal strip having a smaller transverse dimension than that of each metal plane strip.Type: GrantFiled: July 26, 1993Date of Patent: April 25, 1995Assignees: Shinko Electric Industries Co., Ltd., Intel CorporationInventors: Hirofumi Fujii, Yoshiki Takeda, Mitsuharu Shimizu
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Patent number: 5389816Abstract: A metal-core-type multi-layer lead frame adapted to be used for a semiconductor device includes a metal core plate on which a semiconductor chip is to be mounted. A plurality of signal lines are formed on the metal core plate. A metal plane, such as a power supply plane or a ground plane, is laminated on the signal lines, through an insulating layer, so that an outer peripheral edge of said metal core plate is uncovered to expose the outer portion of the respective signal lines. A lead frame body has a plurality of leads which are electrically connected to the respective signal lines at the outer peripheral edge of the metal core plate.Type: GrantFiled: October 22, 1993Date of Patent: February 14, 1995Assignee: Shinko Electric Industries Co., Ltd.Inventors: Mitsuharu Shimizu, Masato Tanaka
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Patent number: 5293301Abstract: A lead frame to be used for a semiconductor device, comprising: a heat sink having a peripheral area and a central projected land on which a semiconductor chip is to be mounted. The heat sink has a relatively good heat radiating characteristic. A plurality of inner leads are provided, each having an inner end superimposed on the peripheral area of the heat sink by an insulating material. A semiconductor chip has a chip surface on which a junction pattern is arranged, and is mounted on the projected land of the heat sink by an insulating adhesive so that the chip surface faces the projected land. TAB leads are provided for electrically connecting the semiconductor chip to the inner leads, and a sealing resin hermetically seals at least the semiconductor chip.Type: GrantFiled: November 27, 1991Date of Patent: March 8, 1994Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masato Tanaka, Katsuya Fukase, Mitsuharu Shimizu, Toshiyuki Murakami
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Patent number: 5291060Abstract: A multi-layer lead frame is provided with a lead frame body made of a metal strip and having a plurality of inner leads including respective tips which define an opening. A power supply metal plane is adhered to the inner leads and a ground metal plane is adhered to the power supply metal plane by insulative adhesive layers. These metal planes are provided with first wire bonding areas and through holes in the vicinity thereof. A semiconductor device comprises such a multi-layer lead frame, a semiconductor chip mounted on a stage thereof, bonding-wires electrically connecting the chip to the areas, and a resin integrally molding the multi-layer lead frame, the chip, and the bonding-wires in such a manner that the through holes are filled with the resin.Type: GrantFiled: December 3, 1992Date of Patent: March 1, 1994Assignees: Shinko Electric Industries Co., Ltd., Intel Corp.Inventors: Mitsuharu Shimizu, Yoshiki Takeda, Hirofumi Fujii
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Patent number: 5281556Abstract: A process for manufacturing a multi-layer semiconductor lead frame comprising the step of adhering a lead frame strip to a metal power supply plane strip and a metal ground plane strip.Type: GrantFiled: May 16, 1991Date of Patent: January 25, 1994Assignee: Shinko Electric Industries Co., Ltd.Inventors: Mitsuharu Shimizu, Yoshiki Takeda
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Patent number: 5237202Abstract: A multi-layer lead frame is provided with a lead frame body made of a metal strip and having a plurality of inner leads including respective tips which define an opening. A power supply metal plane is adhered to the inner leads and a ground metal plane is adhered to the power supply metal plane by insulative adhesive layers. These metal planes are provided with first wire bonding areas and through holes in the vicinity thereof. A semiconductor device comprises such a multi-layer lead frame, a semiconductor chip mounted on a stage thereof, bonding-wires electrically connecting the chip to the areas, and a resin integrally molding the multi-layer lead frame, the chip, and the bonding-wires in such a manner that the through holes are filled with the resin.Type: GrantFiled: December 9, 1991Date of Patent: August 17, 1993Assignees: Shinko Electric Industries Co., Ltd, Intel CorporationInventors: Mitsuharu Shimizu, Yoshiki Takeda, Hirofumi Fujii
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Patent number: 5235209Abstract: A multi-layer lead frame for a semiconductor device comprises a lead frame body made of a metal strip having a first opening and a plurality of inner leads having respective innertips which define the opening. A metal plane independent from the lead frame body and adhered to the inner leads by an insulation adhesive film, has an inner periphery defining a second opening corresponding to the first opening. The inner periphery of the insulation film protrudes slightly from the inner tips of the inner leads.Type: GrantFiled: September 3, 1991Date of Patent: August 10, 1993Assignees: Shinko Electric Industries Co., Ltd., Intel Corp.Inventors: Mitsuharu Shimizu, Yoshiki Takeda, Hirofumi Fujii
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Patent number: 5231756Abstract: A process for manufacturing a multi-layer lead frame for a semiconductor device comprises two metal plains being adhered to each other via an insulation piece. An insulation strip is punched to cut the insulation piece, which is preliminary adhered to a metal strip. The metal strip is then punched to cut and remove the metal plane, which is then laminated and heat-pressed to another metal strip. After completely adhered, the other metal strip is punched to remove a multi-layer lead frame.Type: GrantFiled: October 13, 1992Date of Patent: August 3, 1993Assignees: Shinko Electric Industries Co., Ltd., Intel Corp.Inventors: Masakuni Tokita, Akira Kobayashi, Shinichi Yamakawa, Mitsuharu Shimizu, Norihiro Masuda
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Patent number: 5070390Abstract: A semiconductor device comprising a chip having a plurality of electrodes, a lead frame including a plurality of leads, a tape carrier having an insulative base film and a plurality of conductive patterns formed on the base film, one of the conductive patterns being used as a ground line. The electrodes of the chip are electrically connected to the respective leads of the lead frame via the respective conductive patterns of the tape carrier, a molded resin is used for hermetically and integrally sealing at least the chip and the tape carrier, and a conductive pad is arranged in the vicinity of the conductive patterns of the tape carrier and is electrically connected to the ground line to constitute a microstrip circuit.Type: GrantFiled: May 31, 1990Date of Patent: December 3, 1991Assignee: Shinko Electric Industries Co., Ltd.Inventor: Mitsuharu Shimizu
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Patent number: RE35353Abstract: A process for manufacturing a multi-layer lead frame for a semiconductor device comprises two metal plains being adhered to each other via an insulation piece. An insulation strip is punched to cut the insulation piece, which is preliminary adhered to a metal strip. The metal strip is then punched to cut and remove the metal plane, which is then laminated and heat-pressed to another metal strip. After completely adhered, the other metal strip is punched to remove a multi-layer lead frame.Type: GrantFiled: September 28, 1994Date of Patent: October 22, 1996Assignees: Shinko Electric Ind. Co, Ltd., Intel CorporationInventors: Masakuni Tokita, Akira Kobayashi, Shinichi Yamakawa, Mitsuharu Shimizu, Norihiro Masuda