Abstract: A thermal detector has a thermal detection element in which a physical characteristic changes based on temperature, a light-absorbing member configured and arranged to collect heat and transmit collected heat to the thermal detection element, a support member mounting the thermal detection element on a first side with a second surface facing a cavity, and a support part supporting a portion of the support member. The light-absorbing member is a plate shaped member at least partially contacting a top part of the thermal detection element and having a portion overhanging to an outside from the top part of the thermal detection element in plan view.

Abstract: Detection circuits include a pyroelectric element, source follower circuits that include transistors TN, TP1 in which a detection signal SD from the pyroelectric element is inputted to a gate, first switching elements that interrupt an electric current that flows in the transistors, and a second switching element that interrupts between the pyroelectric element and the gate of the transistor. The second switching element can interrupts a connection between the pyroelectric element and the gate of the transistor before the first switching elements interrupt the electric current that flows in the transistors TN, TP1.

Abstract: A detection circuit includes a pyroelectric element; a first P-type transistor provided between an output node and a low-potential-side power node of the detection circuit, a detection signal being inputted from the pyroelectric element to a gate of the first P-type transistor; and a second P-type transistor provided between a high-potential-side power node and the output node, a gate of the second P-type transistor being set to a reference voltage.

Abstract: A thermal detector has a thermal detection element in which a physical characteristic changes based on temperature, a light-absorbing member configured and arranged to collect heat and transmit collected heat to the thermal detection element, a support member mounting the thermal detection element on a first side with a second surface facing a cavity, and a support part supporting a portion of the support member. The light-absorbing member is a plate shaped member at least partially contacting a top part of the thermal detection element and having a portion overhanging to an outside from the top part of the thermal detection element in plan view.

Abstract: A detection circuit for a heat sensor includes a charge circuit provided between a second power supply node and a detection node of a heat sensing element, and a discharge circuit provided between the detection node and a first power supply node. The discharge circuit has a discharge resistance element and a discharge transistor provided in series between the detection node and the first power supply node.

Abstract: A detection circuit includes a current mirror circuit, a pyroelectric element, a capacitor element and a charging circuit. The pyroelectric element is disposed between a first power supply node and a first node connected to the current mirror circuit. The capacitor element is disposed between the first power supply node and a second node connected to the current mirror circuit. The charging circuit is connected to the current mirror circuit to charge the pyroelectric element and the capacitor element though the current mirror circuit.

Abstract: A method for driving a ferroelectric memory device having a plurality of memory cells that store data and a memory cell for flag is provided. The method includes, upon writing to the plurality of memory cells, the steps of: reading data from the plurality of memory cells and the memory cell for flag; judging as to whether the data readout from the memory cell for flag is specified data; overwriting write data to the plurality of memory cells, and writing reverse data of the specified data to the memory cell for flag, when the data readout from the memory cell for flag is the specified data; and rewriting the data readout from the plurality of memory cells to the plurality of memory cells, and writing the reverse data to the memory cell for flag, when the data readout from the memory cell for flag is the reverse data.

Abstract: A ferroelectric memory device includes: a plurality of bit lines; a plurality of memory cells connected to each of the plurality of bit lines, and each storing “0” data with a smaller amount of readout charge or “1” data with a greater amount of readout charge according to a polarization state; a plurality of data lines; a plurality of charge transfer circuits that connect the plurality of bit lines to the plurality of data lines, respectively, based on a potential on each of the bit lines; a capacitor connected to each of the plurality of data lines for storing negative charge; a positive charge canceling circuit that pulls out positive charge corresponding to the amount of “0” data readout charge from each of the plurality of bit lines; and a sense amplifier that judges data read out from the memory cells.

Abstract: A method for driving a ferroelectric memory device having a plurality of memory cells that store data and a memory cell for flag is provided. The method includes, upon writing to the plurality of memory cells, the steps of: reading data from the plurality of memory cells and the memory cell for flag; judging as to whether the data readout from the memory cell for flag is specified data; overwriting write data to the plurality of memory cells, and writing reverse data of the specified data to the memory cell for flag, when the data readout from the memory cell for flag is the specified data; and rewriting the data readout from the plurality of memory cells to the plurality of memory cells, and writing the reverse data to the memory cell for flag, when the data readout from the memory cell for flag is the reverse data.

Abstract: A ferroelectric memory array includes a plurality of bit lines; a plurality of memory cells connected to the bit lines and storing predetermined data; and a plurality of sense amplifiers provided in correspondence with the bit lines and amplifying data that are read out from the memory cells.

Abstract: A ferroelectric memory device including: a plurality of bit lines; a plurality of memory cells, which are connected to the bit lines, and which store prescribed data; and a sense amplifier, which is connected to a bit line, wherein the sense amplifier includes an op amp, a MOS transistor, and a capacitor, and a first input unit of the op amp is connected to a bit line, a second input unit is connected to a first voltage, an output unit is connected to a gate electrode of the MOS transistor, the MOS transistor is connected between a first node and a second voltage that is lower than the voltage of the first node, and the capacitor is connected between the first node and the bit line.

Abstract: When reading first memory cell data in a ferroelectric memory device, voltage on first bit lines changes. Therefore, controllers turn on first transistors in first read-out voltage generators based on the first bit line voltage, and control the first transistors' channel resistance. When the first transistors turn on, the pre-charged drain voltage lowers and the first read-out voltage generators output the lowered voltage as the first memory cell data's voltage. When reading second memory cell data, a second read-out voltage generator outputs a second transistor's drain voltage that is lowered based on the data as the second memory cell data's voltage. When the second read-out voltage generator outputs the read-out voltage, a reference voltage generator generates a reference voltage equal to the read-out voltage. Because the reference voltage generator has a higher voltage supply capacity than the second read-out voltage generator, the reference voltage is supplied to sense amplifiers.

Abstract: A ferroelectric memory device includes: a plurality of bit lines; a plurality of memory cells connected to each of the plurality of bit lines, and each storing “0” data with a smaller amount of readout charge or “1” data with a greater amount of readout charge according to a polarization state; a plurality of data lines; a plurality of charge transfer circuits that connect the plurality of bit lines to the plurality of data lines, respectively, based on a potential on each of the bit lines; a capacitor connected to each of the plurality of data lines for storing negative charge; a positive charge canceling circuit that pulls out positive charge corresponding to the amount of “0” data readout charge from each of the plurality of bit lines; and a sense amplifier that judges data read out from the memory cells.

Abstract: A ferroelectric memory device includes: a plurality of first bit lines; a plurality of first memory cells that are connected to each of the first bit lines and store first data or second data; a plurality of first read-out voltage generation sections, each of which is connected to each of the plurality of first bit lines, and upon reading data from the plurality of first memory cells, generates a read-out voltage based on the data; a second bit line; a second memory cell that is connected to the second bit line and stores the first data; a second read-out voltage generation section that is connected to the second bit line, and upon reading data from the second memory cell, generates a read-out voltage based on the data; a first reference voltage generation section connected to the second read-out voltage generation section; and a plurality of first sense amplifiers connected to each of the read-out voltage generation sections and the first reference voltage generation section, wherein each of the read-out vol

Abstract: A ferroelectric memory device including: a plurality of bit lines; a plurality of memory cells, which are connected to the bit lines, and which store prescribed data; and a sense amplifier, which is connected to a bit line, wherein the sense amplifier includes an op amp, a MOS transistor, and a capacitor, and a first input unit of the op amp is connected to a bit line, a second input unit is connected to a first voltage, an output unit is connected to a gate electrode of the MOS transistor, the MOS transistor is connected between a first node and a second voltage that is lower than the voltage of the first node, and the capacitor is connected between the first node and the bit line.

Abstract: A ferroelectric memory device characterized in comprising: a voltage source for generating a predetermined voltage; a first bit line and a second bit line; a first ferroelectric capacitor having one end electrically connected to the first bit line; a first resistance provided between the first bit line and the voltage source; a second ferroelectric capacitor having one end electrically connected to the second bit line; a second resistance provided between the second bit line and the voltage source; and a sense amplifier that judges data written in the first ferroelectric capacitor based on a potential on the first bit line, according to a timing at which a potential on the second bit line changes when the predetermined voltage is supplied to the first bit line and the second bit line.

Abstract: A ferroelectric memory device equipped with: a voltage source for generating a predetermined voltage; a first ferroelectric capacitor having one end electrically connected to a first bit line; a first resistance having a first resistance value, provided between the first bit line and the voltage source; a second ferroelectric capacitor having one end electrically connected to a second bit line; a second resistance having a second resistance value different from the first resistance value, provided between the second bit line and the voltage source; and a sense amplifier that judges data written in the first ferroelectric capacitor by comparing a potential on the first bit line with a potential on the second bit line when the predetermined voltage is supplied to the first bit line and the second bit line.

Abstract: A ferroelectric memory device equipped with a plurality of memory cells and a control section that stores memory data indicated by a data signal when a write control signal changes from a first logical value to a second logical value, the ferroelectric memory device wherein, when the write control signal indicates the first logical value, the control section writes preliminary data in a first memory cell, and when the write control signal changes from the first logical value to the second logical value, the control section retains the preliminary data in the first memory cell, or writes the memory data in the first memory cell to store the memory data in the first memory cell.

Abstract: A ferroelectric memory is provided including a ferroelectric capacitor having an end electrically coupled to a bit line; a power source generating a predetermined voltage; a resistance formed between the bit line and the power source; and a switch installed in series with the resistor, and switching whether a predetermined voltage is applied to the bit line via the resistor or not. The voltage source preferably generates a driving voltage driving the ferroelectric memory, a voltage between the resistive voltage of the ferroelectric capacitor and the driving voltage driving the ferroelectric memory, or a voltage that is less than the coercive voltage of the ferroelectric capacitor.

Abstract: A ferroelectric memory array includes a plurality of bit lines; a plurality of memory cells connected to the bit lines and storing predetermined data; and a plurality of sense amplifiers provided in correspondence with the bit lines and amplifying data that are read out from the memory cells.