Patents by Inventor Mitsuhisa Watanabe

Mitsuhisa Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090184430
    Abstract: Semiconductor device 1 includes: first wiring board 5 provided with a plurality of external terminals 9 on the under surface thereof; first semiconductor chip 3 with the under surface thereof mounted on the upper surface of first wiring board 5; and second semiconductor chip 10 with the under surface thereof mounted on the upper surface of first semiconductor chip 3. On the upper surface of first wiring board 5, connecting pad 6a and connecting pad 6b are provided, while connecting pad 6a is electrically connected with the under surface of first semiconductor chip 3 and connecting pad 6b is arranged closely to an end portion of first semiconductor chip 3. Connecting pad 6a and connecting pad 6b are electrically connected with external terminals 9.
    Type: Application
    Filed: January 7, 2009
    Publication date: July 23, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuhisa WATANABE, Ichiro ANJOH
  • Publication number: 20090166863
    Abstract: A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality of semiconductor chips; preparing a plurality of pre-cut substrates each including a substrate body capable of being cut along corresponding one of cutting lines into a pair of same structured substrate pieces, connection pads provided on a top surface of the substrate body, and external terminals formed on a bottom surface of the substrate body and connected to the connection pads; mounting the pre-cut substrates onto the wafer while the cutting lines of the pre-cut substrates match the dicing lines; and simultaneously dicing the wafer and the pre-cut substrates along the dicing lines matching the cutting lines.
    Type: Application
    Filed: December 18, 2008
    Publication date: July 2, 2009
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
  • Publication number: 20090020873
    Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 ?m or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 22, 2009
    Applicant: ELPIDA MEMORY, INC
    Inventors: Mitsuhisa Watanabe, Ichiro Anjoh
  • Publication number: 20090020874
    Abstract: A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring.
    Type: Application
    Filed: July 18, 2008
    Publication date: January 22, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuhisa WATANABE, Ichiro ANJOH
  • Publication number: 20090014874
    Abstract: A semiconductor apparatus includes a semiconductor chip, a wired board, a plurality of bump electrodes, a plurality of external terminals, and insulating material. The semiconductor chip includes a plurality of electrode pads arranged in a central area on one surface. The wired board is arranged as facing one surface of the semiconductor chip, and includes a wiring. The bump electrode is provided between surfaces at which the semiconductor chip and the wired board face each other, and electrically connects the electrode pad and the wiring. The external terminal corresponds to a plurality of bump electrodes, and is mounted on the wired board. The insulating material is provided between the semiconductor chip and the wired board, and covers at least a connection part between the bump electrode and the wiring.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 15, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuhisa WATANABE, Ichiro ANJO
  • Publication number: 20090008798
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Application
    Filed: September 15, 2008
    Publication date: January 8, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Patent number: 7395847
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: July 8, 2008
    Assignee: Fujitsu Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Patent number: 7109561
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: September 19, 2006
    Assignee: Fujitsu Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Publication number: 20050221588
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Application
    Filed: March 10, 2005
    Publication date: October 6, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Publication number: 20050221587
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Application
    Filed: March 10, 2005
    Publication date: October 6, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Publication number: 20050221589
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Application
    Filed: March 10, 2005
    Publication date: October 6, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Patent number: 6951800
    Abstract: A method of making a semiconductor device includes a back-grinding step of grinding a back surface of a semiconductor substrate, a dicing step of dicing the semiconductor substrate along predetermined dicing lines so as to make pieces of semiconductor devices after the back-grinding step, and a laser exposure step of shining laser light on the back surface of the semiconductor substrate after the back-grinding step so as to remove grinding marks generated by the back-grinding step.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: October 4, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshiaki Shinjo, Yuzo Shimobeppu, Kazuo Teshirogi, Kazuhiro Yoshimoto, Eiji Yoshida, Noboru Hayasaka, Mitsuhisa Watanabe
  • Publication number: 20050167812
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Application
    Filed: February 23, 2005
    Publication date: August 4, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Patent number: 6902944
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: June 7, 2005
    Assignee: Fujitsu Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Publication number: 20050085171
    Abstract: A flat-object holder can hold a flat object-and-frame assembly, and the holder has the flat object fixed to the frame with protection tape. The flat-object holder includes at least a flat object supporting area for fixedly holding the flat object via the protection tape by applying a suction force, and a frame fixing area for fastening the frame. The flat-object holder bearing the flat object-and-frame assembly can be fixedly held by a selected chuck table by applying a negative pressure to the flat object supporting area. The flat-object holder can transfer and put the flat object-and-frame assembly in a container. Thus, no matter how thin the flat object may be, it can be handled without the fear of breaking.
    Type: Application
    Filed: November 12, 2004
    Publication date: April 21, 2005
    Inventors: Yuzo Shimobeppu, Kazuo Teshirogi, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Takashi Mori, Koichi Yajima, Yusuke Kimura
  • Patent number: 6869819
    Abstract: A high-contrast image recognition can be performed by recognizing an image of a recognition mark from a back surface of a wafer by a visible-light camera by irradiating a visible light from a circuit pattern surface of a silicon substrate. A thickness of the silicon substrate is set to 5 ?m to 50 ?m. A white or visible light having a wavelength equal to or less than 800 nm is irradiated onto the circuit-pattern forming surface of the substrate. A visible light that has transmitted through the silicon substrate is received by a visible-light camera on a side of a back surface of the silicon substrate. An image of a recognition mark formed on the circuit-pattern forming surface of the silicon substrate is recognized by the visible-light camera.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: March 22, 2005
    Assignee: Fujitsu Limited
    Inventors: Mitsuhisa Watanabe, Yoshikazu Kumagaya, Akira Takashima
  • Patent number: 6837776
    Abstract: A flat-object holder can hold a flat object-and-frame assembly, and the holder has the flat object fixed to the frame with protection tape. The flat-object holder includes at least a flat object supporting area for fixedly holding the flat object via the protection tape by applying a suction force, and a frame fixing area for fastening the frame. The flat-object holder bearing the flat object-and-frame assembly can be fixedly held by a selected chuck table by applying a negative pressure to the flat object supporting area. The flat-object holder can transfer and put the flat object-and-frame assembly in a container. Thus, no matter how thin the flat object may be, it can be handled without the fear of breaking.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: January 4, 2005
    Assignees: Fujitsu Limited, Disco Corporation
    Inventors: Yuzo Shimobeppu, Kazou Teshirogi, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Takashi Mori, Koichi Yajima, Yusuke Kimura
  • Publication number: 20040161882
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Application
    Filed: February 6, 2004
    Publication date: August 19, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Kazuo TESHIROGI, Yuzo SHIMOBEPPU, Kazuhiro YOSHIMOTO, Mitsuhisa WATANABE, Yoshiaki SHINJO, Eiji YOSHIDA, Noboru HAYASAKA
  • Patent number: 6750074
    Abstract: The present invention relates to a method of manufacturing a semiconductor substrate including the back grind step, the dicing step, the pick up step, and the die bonding step of the wafer; and to a semiconductor substrate jig used in such method. The object of the present invention is to mitigate the effect and to prevent damage caused by the lack of strength in thinned semiconductor substrates. A jig with an outer frame 21, and a rubber film 22 arranged within the outer frame 21 and having increasing and decreasing body size while deforming its shape by supplying air therein are provided. As the volume of the rubber film 22 increases, the wafer-fixing jig 20 deforms the rubber film and allows the tapes 2 and 6 arranged between the wafer 1 and the rubber film 22A to be pushed toward the wafer 1 gradually from the center outward. The attachment step, the back grind step, the tape reapplication step, the pick up step and the die bonding step are conducted using such wafer-fixing jig.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 15, 2004
    Assignee: Fujitsu Limited
    Inventors: Kazuo Teshirogi, Yuzo Shimobeppu, Kazuhiro Yoshimoto, Mitsuhisa Watanabe, Yoshiaki Shinjo, Eiji Yoshida, Noboru Hayasaka
  • Publication number: 20030224540
    Abstract: A high-contrast image recognition can be performed by recognizing an image of a recognition mark from a back surface of a wafer by a visible-light camera by irradiating a visible light from a circuit pattern surface of a silicon substrate. A thickness of the silicon substrate is set to 5 &mgr;m to 50 &mgr;m. A white or visible light having a wavelength equal to or less than 800 nm is irradiated onto the circuit-pattern forming surface of the substrate. A visible light that has transmitted through the silicon substrate is received by a visible-light camera on a side of a back surface of the silicon substrate. An image of a recognition mark formed on the circuit-pattern forming surface of the silicon substrate is recognized by the visible-light camera.
    Type: Application
    Filed: December 18, 2002
    Publication date: December 4, 2003
    Applicant: Fujitsu Limited
    Inventors: Mitsuhisa Watanabe, Yoshikazu Kumagaya, Akira Takashima