Patents by Inventor Mitsuo Ariie
Mitsuo Ariie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10348248Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.Type: GrantFiled: June 7, 2018Date of Patent: July 9, 2019Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kiichiro Takenaka, Masahiro Ito, Masakazu Hori, Mitsuo Ariie, Hayato Nakamura, Satoshi Arayashiki, Hidetoshi Matsumoto, Tsuyoshi Sato, Satoshi Tanaka
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Publication number: 20180287565Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.Type: ApplicationFiled: June 7, 2018Publication date: October 4, 2018Inventors: Kiichiro Takenaka, Masahiro Ito, Masakazu Hori, Mitsuo Ariie, Hayato Nakamura, Satoshi Arayashiki, Hidetoshi Matsumoto, Tsuyoshi Sato, Satoshi Tanaka
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Patent number: 10020779Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.Type: GrantFiled: August 30, 2016Date of Patent: July 10, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kiichiro Takenaka, Masahiro Ito, Masakazu Hori, Mitsuo Ariie, Hayato Nakamura, Satoshi Arayashiki, Hidetoshi Matsumoto, Tsuyoshi Sato, Satoshi Tanaka
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Patent number: 9577580Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.Type: GrantFiled: August 30, 2016Date of Patent: February 21, 2017Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kiichiro Takenaka, Masahiro Ito, Masakazu Hori, Mitsuo Ariie, Hayato Nakamura, Satoshi Arayashiki, Hidetoshi Matsumoto, Tsuyoshi Sato, Satoshi Tanaka
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Publication number: 20170047894Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.Type: ApplicationFiled: August 30, 2016Publication date: February 16, 2017Inventors: Kiichiro Takenaka, Masahiro Ito, Masakazu Hori, Mitsuo Ariie, Hayato Nakamura, Satoshi Arayashiki, Hidetoshi Matsumoto, Tsuyoshi Sato, Satoshi Tanaka
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Patent number: 9559654Abstract: Disclosed is a power amplification module which has a comparatively small size and is capable of adjusting the rising characteristic of a gain. The power amplification module includes a first gain control current generation circuit which generates a first gain control current changing with a control voltage, a first bias current generation circuit which generates a first bias current according to the first gain control current, a gain control voltage generation circuit which generates a gain control voltage changing with the control voltage, a first transistor which is emitter-grounded and in which an input signal and the first bias current are supplied to a base thereof, and a second transistor which is cascode-connected to the first transistor and in which the gain control voltage is supplied to a base thereof and a first output signal obtained by amplifying the input signal is output from a collector thereof.Type: GrantFiled: October 22, 2014Date of Patent: January 31, 2017Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hayato Nakamura, Mitsuo Ariie, Tadashi Matsuoka, Tsutomu Onaro
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Publication number: 20160373069Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.Type: ApplicationFiled: August 30, 2016Publication date: December 22, 2016Inventors: Kiichiro Takenaka, Masahiro Ito, Masakazu Hori, Mitsuo Ariie, Hayato Nakamura, Satoshi Arayashiki, Hidetoshi Matsumoto, Tsuyoshi Sato, Satoshi Tanaka
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Patent number: 9461602Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.Type: GrantFiled: July 10, 2014Date of Patent: October 4, 2016Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kiichiro Takenaka, Masahiro Ito, Masakazu Hori, Mitsuo Ariie, Hayato Nakamura, Satoshi Arayashiki, Hidetoshi Matsumoto, Tsuyoshi Sato, Satoshi Tanaka
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Publication number: 20150130537Abstract: Disclosed is a power amplification module which has a comparatively small size and is capable of adjusting the rising characteristic of a gain. The power amplification module includes a first gain control current generation circuit which generates a first gain control current changing with a control voltage, a first bias current generation circuit which generates a first bias current according to the first gain control current, a gain control voltage generation circuit which generates a gain control voltage changing with the control voltage, a first transistor which is emitter-grounded and in which an input signal and the first bias current are supplied to a base thereof, and a second transistor which is cascode-connected to the first transistor and in which the gain control voltage is supplied to a base thereof and a first output signal obtained by amplifying the input signal is output from a collector thereof.Type: ApplicationFiled: October 22, 2014Publication date: May 14, 2015Inventors: Hayato Nakamura, Mitsuo Ariie, Tadashi Matsuoka, Tsutomu Onaro
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Publication number: 20150035607Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.Type: ApplicationFiled: July 10, 2014Publication date: February 5, 2015Inventors: Kiichiro Takenaka, Masahiro Ito, Masakazu Hori, Mitsuo Ariie, Hayato Nakamura, Satoshi Arayashiki, Hidetoshi Matsumoto, Tsuyoshi Sato, Satoshi Tanaka
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Patent number: 7548118Abstract: A semiconductor device 1 includes a plurality of amplifier circuits 2 connected in parallel between an input terminal RFin and an output terminal RFout. Each of the amplifier circuits 2 includes an HBT 3, an oscillation stabilizing circuit 4 connected between the input terminal RFin and a base B of the HBT 3, and a ballast resistor 5 connected between a bias terminal Bin and the base B of the HBT 3. The oscillation stabilizing circuit 4 includes a resistor 6 and a capacitor 7 connected in parallel. Thus, thermorunaway of the HBT 3 can be prevented using the ballast resistor 5, and the stability against oscillation can be improved using the oscillation stabilizing circuit 4 even at low frequencies.Type: GrantFiled: May 24, 2007Date of Patent: June 16, 2009Assignee: Murata Manufacturing Co., Ltd.Inventors: Mitsuo Ariie, Yasutaka Sugimoto
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Publication number: 20070222033Abstract: A semiconductor device 1 includes a plurality of amplifier circuits 2 connected in parallel between an input terminal RFin and an output terminal RFout. Each of the amplifier circuits 2 includes an HBT 3, an oscillation stabilizing circuit 4 connected between the input terminal RFin and a base B of the HBT 3, and a ballast resistor 5 connected between a bias terminal Bin and the base B of the HBT 3. The oscillation stabilizing circuit 4 includes a resistor 6 and a capacitor 7 connected in parallel. Thus, thermorunaway of the HBT 3 can be prevented using the ballast resistor 5, and the stability against oscillation can be improved using the oscillation stabilizing circuit 4 even at low frequencies.Type: ApplicationFiled: May 24, 2007Publication date: September 27, 2007Inventors: Mitsuo Ariie, Yasutaka Sugimoto
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Publication number: 20030042601Abstract: An electronic module having a semiconductor element and filters provided on a base substrate. The filters have an impedance conversion function and are directly connected to the semiconductor element without the aid of a matching circuit. Since no matching circuit is required between the semiconductor element and the filters, the electronic module can be made smaller and signal transmission loss can be suppressed.Type: ApplicationFiled: August 28, 2002Publication date: March 6, 2003Inventors: Mitsuo Ariie, Yutaka Ida, Yoshikazu Yagi
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Patent number: 5973576Abstract: A low-powered mixer that is operable at a low voltage by a single positive power supply. A predetermined voltage and a first data signal Ss1 superimposed on the predetermined voltage are input into the drain D of an FET Q1, while a first carrier signal Sc1 is input into the FET Q1's gate G. The FET Q1 thus generates a first mixed signal So1 by mixing the first data signal Ss1 and the first carrier signal Sc1. A predetermined voltage and a second data signal Ss2 superimposed on the predetermined voltage are input into the FET Q2's drain D, while a second carrier signal Sc2 is input into the FET Q2's gate G. The FET Q2 thus generates a second mixed signal So2 by mixing the second data signal Ss2 and the second carrier signal Sc2. A capacitor C5 causes the sources S of the FETs Q1 and Q2 to float for DC and to be grounded for AC.Type: GrantFiled: November 7, 1997Date of Patent: October 26, 1999Assignee: Murata Manufacturing Co., Ltd.Inventor: Mitsuo Ariie
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Patent number: 5717364Abstract: A small and inexpensive mixer that does not require a choke inductor and a large-capacitance capacitor. The mixer has a FET. The FET's source is grounded via a capacitor and is also connected to a power-supply terminal. The FET's gate is coupled to a bias voltage and also connected to a gate input terminal via a capacitor. The FET's drain is connected to an output terminal via a capacitor. A modulating signal is input into the power-supply terminal, and a local signal is input into the gate input terminal, so that a modulated signal is output from the output terminal.Type: GrantFiled: October 17, 1996Date of Patent: February 10, 1998Assignee: Murata Manufacturing Co. Ltd.Inventors: Mitsuo Ariie, Hiroaki Tanaka
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Patent number: 5686870Abstract: A low-powered mixer that is operable at a low voltage by a single positive power supply. A predetermined voltage and a first data signal Ss1 superimposed on the predetermined voltage are input into the drain D of an FET Q1, while a first carrier signal Sc1 is input into the FET Q1's gate G. The FET Q1 thus generates a first mixed signal So1 by mixing the first data signal Ss1 and the first carrier signal Sc1. A predetermined voltage and a second data signal Ss2 superimposed on the predetermined voltage are input into the FET Q2's drain D, while a second carrier signal Sc2 is input into the FET Q2's gate G. The FET Q2 thus generates a second mixed signal So2 by mixing the second data signal Ss2 and the second carrier signal Sc2. A capacitor C5 causes the sources S of the FETs Q1 and Q2 to float for DC and to be grounded for AC.Type: GrantFiled: July 25, 1996Date of Patent: November 11, 1997Assignee: Murata Manufacturing Co., Ltd.Inventor: Mitsuo Ariie
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Patent number: 5680078Abstract: A voltage and a data signal superimposed on the voltage are input to the drain of an FET and a carrier signal is input to the gate of the FET. The FET mixes the data signal and the carrier signal to generate the mixed signal. Two capacitors are connected between the source and ground for blocking direct current and passing alternating current.Type: GrantFiled: July 9, 1996Date of Patent: October 21, 1997Assignee: Murata Manufacturing Co., Ltd.Inventor: Mitsuo Ariie