Patents by Inventor Mitsuo Tanaka

Mitsuo Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5696006
    Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: December 9, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takehiro Hirai, Masahiro Nakatani, Mitsuo Tanaka, Akihiro Kanda
  • Patent number: 5406106
    Abstract: A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar transistor, a polysilicon film as a conductive film is laid on the entire substrate and selectively etched to form electrodes. In a MIS transistor, the protection film of the silicon nitride film serves as a gate insulator film and the protection film of the polysilicon film serves as a gate electrode. Accordingly, contamination to the gate insulator film at formation of contact holes of the bipolar transistor is prevented, and an excellent semiconductor with Bi-MOS structure is manufactured with low cost.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: April 11, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takehiro Hirai, Masahiro Nakatani, Mitsuo Tanaka, Akihiro Kanda
  • Patent number: 5402220
    Abstract: A fixing device for an image forming apparatus and having a heating member facing a sheet transport path. The heating member has a number of heating portions which are separate in a direction perpendicular to an intended direction of sheet transport. The heating portions are selectively driven in matching relation to a toner image carried on a sheet.
    Type: Grant
    Filed: August 24, 1993
    Date of Patent: March 28, 1995
    Assignee: Ricoh Company, Ltd.
    Inventors: Mitsuo Tanaka, Tsuneo Kurotori, Takashi Bisaiji, Takeshi Takemoto, Kohichiro Jinnai, Toshio Kawakubo
  • Patent number: 5394231
    Abstract: An image forming apparatus capable of forming both of erasable images and images to be stored, and increasing the number of times that a single sheet with an image can be repetitively decolorized and reused. The apparatus includes a photoconductive element for electrostatically forming a latent image representative of image data. A developing device develops the latent image formed on the photoconductive element by either of an ordinary undecolorizable toner and a decolorizable toner.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: February 28, 1995
    Assignee: Ricoh Company, Ltd.
    Inventors: Kazuhisa Sudo, Mitsuo Tanaka, Chikara Imai, Koji Suzuki, Norimasa Sohmiya, Sadao Takahashi
  • Patent number: 5331198
    Abstract: The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.
    Type: Grant
    Filed: August 5, 1992
    Date of Patent: July 19, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Mitsuo Tanaka, Takehiro Hirai, Masahiro Nakatani
  • Patent number: 5323054
    Abstract: In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: June 21, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Mitsuo Tanaka, Takehiro Hirai, Masahiro Nakatani
  • Patent number: 5318917
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating films extending on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion lay
    Type: Grant
    Filed: February 10, 1993
    Date of Patent: June 7, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Yoshiro Fujita, Takehiro Hirai, Mitsuo Tanaka, Hideya Esaki
  • Patent number: 5301031
    Abstract: A display apparatus using a matrix display panel, such as a liquid crystal panel, for converting the number of scanning lines to be displayed to a number that can be accommodated on a panel having a smaller number of scanning lines. The apparatus includes a control circuit which produces control signals in synchronism with the input video signal, horizontal and vertical scanning circuits each including a shift register operated by the control circuit, and a display panel which is formed of a matrix arrangement of pixels that are driven selectively by the scanning circuits. The apparatus further includes a circuit which halts the operation of the vertical shift register at a certain interval within the effective scanning period of the vertical scanning circuit so as to extract vertical shift clocks, thereby removing the vertical shift clocks within the effective display period of the video signal, thereby extracting periodically extracting scanning lines.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: April 5, 1994
    Assignee: Hitachi Ltd.
    Inventors: Masahiro Eto, Nobuaki Kabuto, Mitsuo Tanaka
  • Patent number: 5204274
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating extending films on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion lay
    Type: Grant
    Filed: August 29, 1991
    Date of Patent: April 20, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Yoshiro Fujita, Takehiro Hirai, Mitsuo Tanaka, Hideya Esaki
  • Patent number: 5162252
    Abstract: The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31).The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.
    Type: Grant
    Filed: December 17, 1991
    Date of Patent: November 10, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Mitsuo Tanaka, Takehiro Hirai, Masahiro Nakatani
  • Patent number: 5132720
    Abstract: A method of forming a two-sided print in an image forming apparatus comprises the steps of forming images on first sides of L recording sheets, leaving M recording sheets having images printed on the first sides thereof in the transport path with a non-stacked arrangement, where M.gtoreq.2, and sequentially forming images on the first sides of N-L recording sheets and forming images on second sides of N recording sheets in a predetermined sequence dependent on values of L, M and N.
    Type: Grant
    Filed: April 1, 1991
    Date of Patent: July 21, 1992
    Assignee: Ricoh Company, Ltd.
    Inventors: Hidekatsu Kioka, Mitsuo Tanaka
  • Patent number: 5132719
    Abstract: A method for forming a duplex print, in which a recording sheet has images formed on both sides thereof, includes steps of: setting an interleave number depending on a size of the recording sheet; forming the duplex prints under a condition where the number of the recording sheets located in a transport path is equal to or less than the interleave number; determining whether or not a size of the recording sheet supplied from a paper supplying unit is changed; changing the interleave number to a minimum interleave number when the size of the recording sheet is changed; forming the duplex prints with respect to the new sized recording sheet under a condition where the number of the recording sheet located in the transport path is equal to or less than the minimum interleave number. The present invention also provides an apparatus for forming a duplex print, which operates in accordance with the method for forming a duplex print.
    Type: Grant
    Filed: January 30, 1991
    Date of Patent: July 21, 1992
    Assignee: Ricoh Company, Ltd.
    Inventors: Hidekatsu Kioka, Mitsuo Tanaka
  • Patent number: 5122177
    Abstract: A glass sheet is heated nearly to its softening point while being passed through a heating furnace. The heated glass sheet is then clamped at its peripheral edge between first and second molds. Thereafter, a third mold is pressed against a central region of the glass sheet with the peripheral edge thereof clamped, thereby to project the central region from one side to the other side thereof. The glass sheet is thus pressed to a desired highly curved shape with no wrinkles or cracks developed therein. The glass sheet is clamped and pressed by a pressing apparatus which includes a fixed concave ring mold as the first mold, and a movable convex mold comprising a peripheral mold assembly as the second mold and a central mold member as the third mold. The glass sheet thus curved is typically used as a front or rear window glass sheet for automobiles.
    Type: Grant
    Filed: January 7, 1991
    Date of Patent: June 16, 1992
    Assignee: Nippon Sheet Glass Co., Ltd.
    Inventors: Hideo Yoshizawa, Yasuhiko Saikawa, Mitsuo Tanaka
  • Patent number: D325195
    Type: Grant
    Filed: March 19, 1990
    Date of Patent: April 7, 1992
    Assignee: Seiko Epson Corporation
    Inventor: Mitsuo Tanaka
  • Patent number: D326679
    Type: Grant
    Filed: June 25, 1990
    Date of Patent: June 2, 1992
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuo Tanaka, Hitoshi Igarashi
  • Patent number: D328290
    Type: Grant
    Filed: March 5, 1990
    Date of Patent: July 28, 1992
    Assignee: Seiko Epson Corporation
    Inventor: Mitsuo Tanaka
  • Patent number: D332255
    Type: Grant
    Filed: August 31, 1990
    Date of Patent: January 5, 1993
    Assignee: Seiko Epson Corporation
    Inventor: Mitsuo Tanaka
  • Patent number: D368113
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: March 19, 1996
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuo Tanaka, Toshihiro Hayakawa
  • Patent number: D381320
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: July 22, 1997
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kobayashi, Mitsuo Tanaka
  • Patent number: D388771
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: January 6, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kobayashi, Mitsuo Tanaka