Patents by Inventor Mitsuru Hirao
Mitsuru Hirao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6545572Abstract: This triplate line interfacial connector electrically connects a first triplate line comprised of a first grounding conductor, first dielectric, first power feeding substrate, second dielectric and second grounding conductor, and a second triplate line comprised of a second grounding conductor, third dielectric, second power feeding substrate, fourth dielectric, and third grounding conductor. A patch pattern is formed at a connecting terminal portion of each power feeding line. Two shield spacers each having a through portion around the patch pattern are provided. A first slot is formed at a connecting position between the two triplate lines in the second grounding conductor.Type: GrantFiled: September 7, 2000Date of Patent: April 8, 2003Assignee: Hitachi Chemical Co., Ltd.Inventors: Masahiko Ohta, Mitsuru Hirao, Hisayoshi Mizugaki, Takao Michisaka, Kiichi Kanamaru
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Patent number: 5672897Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.Type: GrantFiled: June 5, 1995Date of Patent: September 30, 1997Assignee: Hitachi, Ltd.Inventors: Atsuo Watanabe, Takahide Ikeda, Kiyoshi Tsukuda, Mitsuru Hirao, Touji Mukai, Tatsuya Kamei
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Patent number: 5512497Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.Type: GrantFiled: July 8, 1994Date of Patent: April 30, 1996Assignee: Hitachi, Ltd.Inventors: Takahide Ikeda, Kouichirou Yamada, Osamu Saito, Masanori Odaka, Nobuo Tamba, Katsumi Ogiue, Atsushi Hiraishi, Atsuo Watanabe, Mitsuru Hirao, Akira Fukami, Masayuki Ohayashi, Tadashi Kuramoto
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Patent number: 5508549Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.Type: GrantFiled: July 25, 1991Date of Patent: April 16, 1996Assignee: Hitachi, Ltd.Inventors: Atsuo Watanabe, Takahide Ikeda, Kiyoshi Tsukuda, Mitsuru Hirao, Touji Mukai, Tatsuya Kamei
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Patent number: 5354699Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.Type: GrantFiled: October 22, 1992Date of Patent: October 11, 1994Assignee: Hitachi, Ltd.Inventors: Takahide Ikeda, Kouichirou Yamada, Osamu Saito, Masanori Odaka, Nobuo Tamba, Katsumi Ogiue, Atsushi Hiraishi, Atsuo Watanabe, Mitsuru Hirao, Akira Fukami, Masayuki Ohayashi, Tadashi Kuramoto
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Patent number: 5144394Abstract: The structure of a MOSFET and a method for fabricating the same is disclosed, with which it is possible to increase the driving capacity. Heretofore there was a problem that no measures were taken against the decrease in the channel width due to bird's beaks produced at the formation of a field oxide film and that the channel width at the completion of the manufacturing process was smaller than that foreseen during the design of the device. To overcome this problem, a MOSFET is provided in which the junction of the source or the drain is extended up to the end portions in the channel direction so that the effective channel width is determined by the width of the junction on the sides, where the junction is not extended up to the end portions in the channel direction.Type: GrantFiled: August 31, 1990Date of Patent: September 1, 1992Assignee: Hitachi, Ltd.Inventors: Mitsuru Hirao, Masataka Minami, Shoji Shukuri
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Patent number: 5072286Abstract: A semiconductor memory device has memory cells each including first and second inverters cross-coupled to each other through first and second interconnecting conductors for forming a bistable circuit and first and second transfer gates connected between the first inverter and address signal conductors and between the second inverter and the address signal conductors, respectively. The first and second interconnecting conductors are arranged substantially point-symmetrically and have at least portions substantially parallel with each other on a surface of a substrate, and IG FETs constituting the first and second inverters have their gate electrodes arranged substantially parallel with one another and extending in a direction substantially perpendicular to the parallel portions of the first and second interconnecting conductors for the cross-coupling on the surface of the substrate.Type: GrantFiled: September 25, 1990Date of Patent: December 10, 1991Assignee: Hitachi, Ltd.Inventors: Masataka Minami, Shoji Shukuri, Mitsuru Hirao, Toshiaki Yamanaka
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Patent number: 5057894Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.Type: GrantFiled: May 23, 1990Date of Patent: October 15, 1991Assignee: Hitachi, Ltd.Inventors: Takahide Ikeda, Kouichirou Yamada, Osamu Saito, Masanori Odaka, Nobuo Tamba, Katsumi Ogiue, Atsushi Hiraishi, Atsuo Watanabe, Mitsuru Hirao, Akira Fukami, Masayuki Ohayashi, Tadashi Kuramoto
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Patent number: 5049967Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from a surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.Type: GrantFiled: December 21, 1990Date of Patent: September 17, 1991Assignee: Hitachi, Ltd.Inventors: Atsuo Watanabe, Takahide Ikeda, Kiyoshi Tsukuda, Mitsuru Hirao, Touji Mukai, Tatsuya Kamei
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Patent number: 4984200Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM which is composed of a memory cell having its high resistance load element and power source voltage line connected with the information storage node of a flip-flop circuit through a conductive layer. At the same fabrication step as that of forming the plate electrode layer of a capacity element over the conductive layer formed on the portion of the information storage node through a dielectric film, an electric field shielding film for shielding the field effect of a data line is formed over the high resistance load element through an inter-layer insulation film.Type: GrantFiled: November 15, 1988Date of Patent: January 8, 1991Assignee: Hitachi, Ltd.Inventors: Ryuichi Saitoo, Osamu Saitoo, Takahide Ikeda, Mitsuru Hirao, Atsushi Hiraishi
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Patent number: 4980744Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.Type: GrantFiled: February 24, 1988Date of Patent: December 25, 1990Assignee: Hitachi, Ltd.Inventors: Atsuo Watanabe, Takahide Ikeda, Kiyoshi Tsukuda, Mitsuru Hirao, Touji Mukai, Tatsuya Kamei
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Patent number: 4921811Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.Type: GrantFiled: March 31, 1988Date of Patent: May 1, 1990Assignee: Hitachi, Ltd.Inventors: Atsuo Watanabe, Takahide Ikeda, Kiyoshi Tsukuda, Mitsuru Hirao, Touji Mukai, Tatsuya Kamei